International Business Machines Corporation

Globalfoundries Inc.

Yufei Li

Hao Yang

Yong Qing Lu

Fan Zhou

Yi Bin Wang

Liang Chen

Ying Chu Wang

Mengze Liao

Jian Tang

Cheng Song

Jiang Yu

Yong Feng Pan

Bo Fan

Hou Gang Li

Yang Liu

Dan Liu

Jian Long Yang

Heng Liu

Jin Jiang

Peng Fei Gou

Guofan Jiang

De Xian Li

Zhi Gui Liu

Yi Fan Lin

ZeQiang Xiao

An approach for efficient booting. The approach loads a firmware into a memory from one or more integrated memories, wherein the one or more integrated memories are flash memories on a motherboard. The approach loads an operating system into the memory from the one or more integrated memories. Responsive to loading the operating system into the memory, the approach mounts one or more root filesystems.

Efficient booting system

Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.

Multi-bit error correction method and apparatus based on a BCH code and memory system

The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

Decoding method, decoding apparatus and decoder

An integrated circuit (IC) can dynamically manage memory communication paths between multiple processors and multiple memory modules. The IC can include upstream logic that performs data conversion and provides memory communication paths between each processor and a corresponding upstream port. An interconnect layer in the IC can be electrically coupled to the upstream ports to multiple downstream ports. An interconnect management processor electrically coupled to the interconnect layer can respond to received commands by executing an allocation program stored in a read-only memory (ROM) that dynamically establishes and terminates memory communication paths between the upstream ports and the downstream ports. A memory interface layer in the IC can be electrically coupled to the downstream ports and to the memory modules, and can provide, through corresponding memory physical interfaces, memory communication paths between the multiple downstream ports and corresponding memory modules.

Elastic memory expansion chip architecture

Latency reduced error correction scheme with error indication function for burst error correction codes

The present invention discloses a digital integrated circuit simulation method and simulator. The method comprises: obtaining a circuit diagram of the digital integrated circuit and a checkpoint in the circuit diagram; determining a point relevant to a boundary between a two-value simulation and a multi-value simulation in the circuit diagram and a state of the relevant point according to the checkpoint; determining a boundary position, as well as a boundary type of the boundary position, of the boundary between the two-value simulation and the multi-value simulation in the circuit diagram according to the relevant point and the state of the relevant point; inserting a conversion circuit at the boundary position according to the boundary type of the boundary position; and modeling and simulating the circuit diagram into which the conversion circuit is inserted. The method and simulator can reduce simulation time and the needed storage resources.

Digital IC simulation

A method, apparatus and decoder for decoding cyclic code are proposed. The decoding method comprises: receiving a transmitted cyclic code; calculating the initial syndrome of the cyclic code; by using the initial syndrome and w prestored successive shift operators, calculating respectively w successive shift syndromes in a w-bit window of the cyclic code in parallel; and detecting/locating error in the cyclic code based on the obtained syndromes. The decoding apparatus corresponds to the above method. And the corresponding decoder is also proposed in this invention. The method, apparatus and decoder according to the invention could process the cyclic code within a window width and thus enhance decoding efficiency in parallel.

Method, apparatus and decoder for decoding cyclic code

The present invention discloses a content addressable memory and a method of searching data thereof. The method includes generating a hash index data item from a received input data item; searching the cache for presence of a row tag of the RAM data row corresponding to the data item of hash index; in response to presence, searching the RAM for a RAM data item corresponding to the input data item according to the corresponding row tag of the RAM data row; in response to absence, searching the RAM for a RAM data item corresponding to the input data item by using the data item of hash index; and in response to finding a RAM data item corresponding to the input data item in the RAM, outputting data corresponding to the RAM data item. The method can accelerate data search in the CAM.

Content addressable memory and method of searching data thereof

Disclosed are a method and apparatus for detecting frame boundary for a data stream received at an Ethernet FEC layer, as well as a decoding method and system for the same. The apparatus for detecting frame boundary may comprise: a buffer for buffering data in a data stream, a length of the data in the buffer being greater than one frame; a syndrome generator for calculating a current syndrome based on a first data item, a second data item, and an intermediate calculation result of a previous syndrome, wherein the first data item is the last bit in a current candidate frame, and the second data item is a bit preceding the current candidate frame; and a comparator for using the current syndrome to check whether the bit preceding the current candidate frame is a frame boundary of an Ethernet FEC layer. The apparatus for detecting frame boundary can improve the speed of frame boundary detection.

Frame boundary detection and decoding

A method and an apparatus for tracking uncertain signals in the simulation of chip design are provided. The method comprises: generating a directed graph which contains sequential logic devices and IO devices from the netlist of chip design, wherein the directed graph illustrates the signal association among the sequential logic devices and IO devices; obtaining the signals related with the sequential logic devices and IO devices from the simulation results, wherein the signals contain a plurality of uncertain signals; and back tracing at least a part of the plurality of uncertain signals along the directed graph to determine the device which firstly generates an uncertain signal. The corresponding apparatus is also provided. With the above method and apparatus, uncertain signals can be traced and their source can be determined, which improves the debugging efficiency.

Method and apparatus for tracking uncertain signals

Growing community of inventors

Shanghai, China

Yufei Li