Applied Materials, Inc.

Yufei Hu

Yu Lei

Kazuya Daito

Yi Xu

Tae Hong Ha

Xuesong Lu

Da He

Andrew Nguyen

Philip Allan Kraus

Xianmin Tang

Dien-Yeh Wu

Tza-Jing Gung

Jallepally Ravi

Feng Chen

Wenjing Xu

Chung Liu

Jiajie Cen

Hui Sun

Gang Shen

He Ren

Zhiyuan Wu

Chong Jiang

Hyman W H Lam

Shi You

Geraldine M Vasquez

Malcolm Emil Delaney

Anup Phatak

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH—NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

Directional selective junction clean with field polymer protections

Methods for selective deposition are described herein. Further, methods for improving selectivity comprising an ammonia plasma pre-clean process are also described. In some embodiments, a silyl amine is used to selectively form a surfactant layer on a dielectric surface. A ruthenium film may then be selectively deposited on a conductive surface. In some embodiments, the ammonia plasma removes oxide contaminations from conductive surfaces without adversely affecting the dielectric surface.

Methods of selective deposition

Embodiments of the disclosure relate to methods of depositing tungsten. Some embodiments of the disclosure provide methods for depositing tungsten which are performed at relatively low temperatures. Some embodiments of the disclosure provide methods in which the ratio between reactant gasses is controlled. Some embodiments of the disclosure provide selective deposition of tungsten. Some embodiments of the disclosure provide methods for depositing tungsten films at a low temperature with relatively low roughness, stress and impurity levels.

Selective tungsten deposition at low temperatures

Methods for pre-cleaning substrates having metal and dielectric surfaces are described. A temperature of a pedestal comprising a cooling feature on which a substrate is located is set to less than or equal to 100° C. The substrate is exposed to a plasma treatment to remove chemical residual and/or impurities from features of the substrate including a metal bottom, dielectric sidewalls, and/or a field of dielectric and/or repair surface defects in the dielectric sidewalls and/or the field of the dielectric. The plasma treatment may be an oxygen plasma, for example, a direct oxygen plasma. Processing tools and computer readable media for practicing the method are also described.

Low-temperature plasma pre-clean for selective gap fill

A method includes receiving a plurality of sets of sensor data associated with a processing chamber of a substrate processing system. Each of the plurality of sets of sensor data comprises a corresponding sensor value of the processing chamber mapped to a corresponding spacing value of the processing chamber. The method further includes providing the plurality of sets of sensor data as input to a trained machine learning model. The method further includes obtaining, from the trained machine learning model, one or more outputs indicative of a health of the processing chamber. The method further includes causing, based on the one or more outputs, performance of one or more corrective actions associated with the processing chamber.

Chamber matching and calibration

Methods for pre-cleaning substrates having metal and dielectric surfaces are described. A substrate comprising a surface structure with a metal bottom, dielectric sidewalls, and a field of dielectric is exposed to a dual plasma treatment in a processing chamber to remove chemical residual and/or impurities from the metal bottom, the dielectric sidewalls, and/or the field of the dielectric and/or repair surface defects in the dielectric sidewalls and/or the field of the dielectric. The dual plasma treatment comprises a direct plasma and a remote plasma.

Dual plasma pre-clean for selective gap fill

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH&#x2014;NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are&#x2014;etched only minimally or not at all.

Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.

Selective tungsten deposition within trench structures

Methods and apparatus for forming an interconnect structure, the method including selectively depositing two or more capping layers atop a top surface of a via within a low-k dielectric layer, wherein the two or more capping layers include a first layer of ruthenium and a second layer of cobalt.

Methods for forming cobalt and ruthenium capping layers for interconnect structures

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Fremont, CA, United States of America

Yufei Hu