Integrated Device Technology, Inc.

Montage Electronics (shanghai) Co., Ltd.

YuFei Gu

Liang Zhang

Howard Chonghe Yang

Zhongyuan Chang

Xuexin Ding

Gang Yan

Lixin Jiang

Li Quan

Zongjie Hu

Qing Ou-yang

The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.

Glitch removal circuit

A voltage/current reference circuit includes a first bipolar transistor and a second bipolar transistor that exhibit a first voltage drop Vand a second voltage drop V, respectively. A first resistor, having a resistance R, is configured to draw a first current equal to (V&#x2212;V)/R. A second resistor, having a resistance R, is configured to draw a second current equal to V/R. A first transistor supplies the first and second currents to the first and second resistors. A second transistor, having a current mirror configuration with respect to the first transistor, directly provides a reference current equal to (V&#x2212;V)/R+V/R. A third transistor, having a current mirror configuration with respect to the first transistor, provides a current equal to the reference current to a third resistor having a resistance Rand a third bipolar transistor that exhibits a third voltage drop V, thereby generating a reference voltage.

Precise voltage/current reference circuit using current-mode technique in CMOS technology

Growing community of inventors

Shanghai, China

YuFei Gu