Altera Corporation

Yuet Li

Ankireddy Nalamalpu

Mahesh K Kumashikar

Atul Maheshwari

Mahesh A Iyer

Md Altaf Hossain

Dheeraj R Subbareddy

Ian Kuon

The present disclosure describes programmable logic that may be operated in a turbo processing mode to cause an ongoing operation to be completed faster than a scheduled completion time. With at least some of the remaining time to the scheduled completion time, power savings may be realized by operating the programmable logic into a deep sleep mode, where configuration memory associated with the programmable logic may be set to a suitable voltage level as to not cause data loss at lower or zero voltage levels but otherwise realize power savings relative to an amount of power consumed during average processing operations.

Workload-dependent integrated circuit operation based on power headroom

Systems or methods of the present disclosure may provide for determining a loadline for operation of a programmable logic fabric where the loadline is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The loadline may be determined using software modeling for the design or configuration. Additionally or alternatively, the loadline may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

Dynamic loadlines for programmable fabric devices

Systems or methods described herein may relate to latch-independent clock gating techniques to enable or disable an internal clock of an integrated circuit device. A programmable logic device includes a clock gating circuit that receives a clock signal and is latch independent. The clock gating circuit includes gating signal circuitry that generates a gating signal based on the clock signal and an enable signal. The clock gating circuit also includes a logic gate that generates a control signal based on the gating signal. The clock gating circuit also includes gated clock generation circuitry that generates a gated clock signal based on the clock signal and the control signal.

Self-gating flops for dynamic power reduction

Systems or methods of the present disclosure may provide efficient power consumption for programmable logic devices based on reducing guardband voltages. A programmable logic device may include circuit monitors to mimic critical paths of an implemented circuit design and generate timing information based on the critical paths. A controller on the programmable logic device may adjust the voltage guardband based on the timing information.

Systems and methods to reduce voltage guardband

Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.

Power management using voltage islands on programmable logic devices

Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

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Fremont, CA, United States of America

Yuet Li