Advanced Micro Devices Corporation

Other

Yuesong He

Kent Kuohua Chang

John JianShi Wang

David H Chi

Effiong Etukudo Ibok

Jiahua Huang

Kenneth Wo-Wai Au

Ken Au

Dae Yeong Joh

Toru Ishigaki

R Lee Tan

Dopant of an n-type is deposited in the channel area of a p-type well of isolated gate floating gate NMOS transistors forming the memory cells of a memory device array connected in a NAND gate architecture. The dopant is provided by a tilt angle around the existing floating gate/control gate structure at the stage of the fabrication process where the floating gate/control structure is in existence, the field oxidation step may also have occurred, and implantation of the source and drain dopants may also have occurred. This forms a retrograde n-type distribution away from the direction of the surface of the substrate in the channel, which is also concentrated laterally toward the centerline axis of the gate structure and decreases towards the opposing source and drain regions. This deposition promotes buried-channel-like performance of the NMOS transistors connected in series in the NAND gate memory architecture. This reduces series resistance of the series-connected floating gate MOS devices, allowing the desired reduction in source/drain dopant levels in order to combat short channel effects.

Method and apparatus for improved performance of flash memory cell devices

In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide by chemical vapor deposition using a silicon containing gas and a mixture of a phosphorus containing gas and a carrier gas, the first polysilicon layer having a thickness from about 800 &angst; to about 1,000 &angst;; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF and SiH Cl ; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

Effect of doped amorphous Si thickness on better poly 1 contact resistance performance for nand type flash memory devices

Polystringers that cause NAND-type memory core cells to malfunction are covered by ONO fence material. ONO fence is removed so that polystringers may then be removed more readily. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. The device is next exposed to an hydrogen-fluoride solution to remove oxide-based materials, particularly ONO fence. Thereafter, the polystringers are exposed and may thus be removed more readily.

Manufacturing process to eliminate ONO fence material in high density NAND-type flash memory devices

In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a core region and a periphery region, the core region including a flash memory cell area and a select gate area and the periphery region including a high voltage transistor area and low voltage transistor area; depositing a first doped amorphous silicon layer over at least a portion of the first oxide layer; depositing a dielectric layer over at least a portion of the first doped amorphous silicon layer; removing portions of the first oxide layer, the first doped amorphous silicon layer, and the dielectric layer in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; growing a second oxide layer over at least a portion of the substrate in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; removing portions of the second oxide layer in the select gate area of the core region and the low voltage transistor area the periphery region; growing a third oxide layer over at least a portion of the substrate in the select gate area of the core region and the low voltage transistor area of the periphery region; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer, the second oxide layer and the third oxide layer; and forming a flash memory cell in the flash memory cell area of the core region, a select gate transistor in the select gate area of the core region, a low voltage transistor in the low voltage transistor area of the periphery region, and a high voltage transistor in the high voltage transistor area of the periphery region.

Method of forming select gate to improve reliability and performance for NAND type flash memory devices

In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer; forming a second polysilicon layer over the insulating layer by depositing an second polysilicon layer having a first thickness, and then using chemical mechanical polishing to form a second polysilicon layer having a second thickness, wherein the second thickness is at least about 25% less than the first thickness; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF,and SiH,; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

Method to elimate silicide cracking for nand type flash memory devices by implanting a polish rate improver into the second polysilicon layer and polishing it

This invention relates to a method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of said device, wherein at least some of the contaminate nitrogen has formed a bond with the surface of the silicon substrate in contact with the gate oxide layer in said gate region, said method comprising: contacting said gate oxide layer and contaminate nitrogen with a gas comprising ozone at a temperature of about 850&deg; C. to about 950&deg; C. for an effective period of time to break said bond; and removing said gate oxide layer and contaminate nitrogen from said surface of said silicon substrate.

Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device

Tunnel oxide degradation is reduced by reducing residual photoresist material in open areas of a mask pattern. Embodiments include detecting residual photoresist in an exposed underlying region of a substrate by x-ray spectroscopy and descumming in response to detected residual photoresist.

Method for manufacturing memory devices

A polysilicon-based floating gate is formed so as to be resistant to oxidation that occurs during multiple thermo-cycles in fabrication. Accordingly, edge erase times in NOR-type memory devices may be minimized. Additionally, manufacture of oxidation resistant floating gates reduces variations in edge erase times among multiple NOR-type memory devices. A layer of amorphous silicon is deposited over a silicon substrate by directing a mixture of silane and a phosphene-helium gas mixture at the surface of the silicon substrate. Later, N+ ions are implanted into the amorphous silicon. The amorphous silicon layer is then etched so as to overlap slightly with regions that will later correspond to the source and drain regions. Next, a lower oxide layer of an ONO dielectric is deposited and the device is heated. A thermo-cycle is eliminated by heating the amorphous silicon during formation of the oxide layer rather than immediately following its deposition. Later, the nitride and oxide layers of the ONO dielectric, a second polysilicon layer, a tungsten silicide layer, and SiON layers are successively formed.

Nitrogen ion implanted amorphous silicon to produce oxidation resistant

A method and apparatus for an integrated circuit on a semiconductor substrate having good metal contact points. A first polysilicon layer is formed onto the substrate, and is etched to provide contact regions to the substrate. An ONO layer is formed onto the first polysilicon layer. A second polysilicon layer is formed onto the ONO layer, and a metal silicide layer is formed onto the second polysilicon layer. The second polysilicon layer and the metal silicide layer are etched at particular locations in order to form contact regions to the first polysilicon layer and to the substrate. A selective layer is formed onto the second polysilicon layer, the selective layer being etch selective with respect to the first polysilicon layer. An interlayer dielectric is formed onto the selective layer. A first etching is performed to provide a contact path through the interlayer dielectric, and then a second etching is performed to provide a contact path through the selective layer. Based on these two contact paths, a contact point can be provided externally to the first polysilicon layer.

Method and apparatus for preventing P1 punchthrough

A layer of polysilicon is deposited over an oxide layer on top of a silicon substrate, with core field oxide and active regions, and patterned. An oxide mask is then added. Next, the oxide mask and the layer of polysilicon are removed from above the core field oxide regions. Next, a second layer of polysilicon is deposited and etched to form polysilicon spacers. Later, an ONO dielectric, a third polysilicon layer, a tungsten silicide layer, and SiON layers are successively formed and patterned. The polysilicon spacers effectively seal any recesses that may occur in the edges of the first polysilicon layer to prevent harboring of subsequently added polysilicon material. Accordingly, NAND-type flash memory core cells cannot be electrically shorted by polysilicon material, so called 'polystringers', present in such recesses.

Poly I spacer manufacturing process to eliminate polystringers in high

This invention relates to a method for forming a low barrier height oxide layer on the surface of a crystalline silicon substrate, comprising: (A) forming spaced field oxide regions on the surface of said crystalline silicon substrate, the space between said field oxide regions comprising a tunnel region; (B) vapor depositing a layer of amorphous silicon on the surface of said field oxide regions and on the surface of said substrate in said tunnel region, the thickness of said layer of amorphous silicon being in the range of about 50 .ANG. to about 100 .ANG.; and (C) oxidizing said layer of amorphous silicon. The oxidized amorphous silicon layer in said tunnel region is a tunnel oxide layer and, in one embodiment, the inventive method includes the step of (D) forming a floating gate over said tunnel oxide layer, said tunnel oxide layer having a barrier height of about 1.6 to about 2.0 eV.

Method for forming a low barrier height oxide layer on a silicon

In one embodiment, the present invention relates to a method of forming a flash memory cell involving the steps of: forming a tunnel oxide on a substrate; forming an in situ phosphorus doped polysilicon layer over the tunnel oxide by low pressure chemical vapor deposition at a temperature between about 610.degree. C. and about 630.degree. C., wherein the in situ phosphorus doped polysilicon layer comprises from about 1.times.10.sup.19 atoms/cm.sup.3 to about 5.times.10.sup.19 atoms/cm.sup.3 of phosphorus; forming an insulating layer over the in situ phosphorus doped polysilicon layer; forming a conductive layer over the insulating layer; etching the in situ phosphorus doped polysilicon layer, the conductive layer and the insulating layer, thereby defining one or more stacked gate structures; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are self-aligned by the stacked gate structures, thereby forming one or more memory cells.

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San Jose, CA, United States of America

Yuesong He