Intel Corporation

Yuenian Yang

Guei-Yuan Lueh

Hong Jiang

Ping Liu

Maxim Lukyanov

Xuefeng Zhang

Xiaoying He

Andrew J Kuzma

Stewart N Taylor

Kaiyu Chen

Julia A Gould

Yuting Yang

Ryan Metcalfe

A processing apparatus is described. The apparatus includes a plurality of execution threads having a first thread space configuration including a first plurality of rows of execution threads to process data in parallel, wherein each thread in a row is dependent on a top neighbor thread in a preceding row, partition logic to partition the plurality of execution threads into a plurality of banks, wherein each bank includes one or more of the first plurality of rows of execution threads and transform logic to transform the first thread space configuration to a second thread space configuration including a second plurality of rows of execution threads to enable the plurality of execution threads in each of the plurality of banks to operate in parallel.

Mechanism to increase thread parallelism in a graphics processor

Embodiments are generally directed to global optimal path determination utilizing parallel processing. An embodiment of an apparatus includes a central processing unit (CPU); a graphical processing unit (GPU), the GPU being capable of a plurality of processing threads; and a memory to store data for a system under evaluation, the system under evaluation including a set of nodes having a first endpoint, a second endpoint, and multiple paths between the first endpoint and the second endpoint. The apparatus is to determine a most energy efficient path between the first endpoint and the second endpoint utilizing parallel processing of a push and relabel graph cut algorithm. Performance of the push and relabel algorithm includes a plurality of process iterations, each process iteration including performance of a relabel operation, a push operation in a first direction, and a push operation in a second direction.

Global optimal path determination utilizing parallel processing

Techniques related to accelerating color conversion are discussed. Such techniques may include generating a converted color value based on an array of ordered coefficients associated with a subsection of a section of a color conversion space and input color channel value offsets within the section of the color conversion space.

Acceleration of color conversion

A computer system may generate a plurality of component kernels, which are to be linked during the runtime. The system may determine whether a combined kernel K is present in response to receiving a first request to retrieve the combined kernel K. The system may compose the combined kernel K from the selected component kernels of the plurality of component kernels during the runtime if the combined kernel is not already present.

Dynamic linking and loading of post-processing kernels

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Folsom, CA, United States of America

Yuenian Yang