International Business Machines Corporation

Yuen H Chan

Antonio R Pelella

John D Davis

Paul Alan Bunce

Rajiv V Joshi

Tobias Werner

Arthur D Tuminaro

William Vincent Huott

Juergen Pille

Donald W Plass

Rolf Sautter

Silke Penth

Ryan T Freese

Jatinder K Wadhwa

David Edward Schmitt

William Robert Reohr

Michael B Kugel

Michael Ju Hyeok Lee

Diana M Henderson

Brian James Yavoich

Pong-Fei Lu

John R Rawlins

Timothy J Charest

Pradip Patel

Daniel Rodko

Uma Srinivasan

James R Struk

Anirudh Devgan

Stefan Payer

Michael J Lee

Otto M Wagner

Qiuyi Ye

Wolfgang Penth

Richard Edward Serton

Ann H Chen

Antonia R Pelella

Shie-ei Wang

Timothy John Slegel

Louis L Hsu

Mark S Farrell

Charles Franklin Webb

Robert C Wong

Louis C Hsu

Raphael C Polig

Joseph M Mosley

Xu Ouyang

Barry Watson Krumm

Jigar Vora

Philip George Shephard, Iii

Walter S Klara

Philip T Wu

Andrew James Bianchi

Ed Seewann

Elspeth Anne Huston

Robert Chi-Foon Wong

Theodore William Kwap

Frank D Jones

Masood Ahmed Khan

Edelmar Seewann

Carlos G Rivadeneira

Rolf H Nijhuis

James E Dickerson

William F Stinson

Anuj Kohli

Kenneth M Lo

Anthony R Pelella

Michael J H Lee

Techniques for a power saving scannable latch output driver in an integrated circuit (IC) are described herein. An aspect includes receiving, by a circuit comprising a scannable latch, a scan signal. Another aspect includes, based on the scan signal being enabled, turning on a scan output driver of the scannable latch, wherein a scan input of the scannable latch propagates through the scannable latch to a scan output based on the scan output driver being turned on. Another aspect includes, based on the scan signal being disabled, turning off the scan output driver, wherein the scan output driver comprises a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET), wherein a gate of the first PFET and a gate of the first NFET are connected to an output of a latch of the scannable latch.

Power saving scannable latch output driver

A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

Dynamic decode circuit with active glitch control

A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Dynamic decode circuit with active glitch control method

A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.

A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Dynamic decode circuit with delayed precharge

A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.

Automated stressing and testing of semiconductor memory cells

A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical 'high' voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical 'low' voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.

Managing semiconductor memory array leakage current

It is provided a memory circuit comprising n inputs; n+1 columns, wherein each column is connected to a plurality of memory cells; wherein the i-th (1&#x2266;i&#x2266;n&#x2212;1) column is configured to be conductive connectable to the i-th input or to the (i+1)-th input or neither to the i-th input nor to the (i+1)-th input; a first FET and a second FET in series configured for connecting the i-th column to a defined voltage level; wherein a first gate signal renders the first FET conductive, if the i-th column is not in conductive connection with the i-th input; wherein a second gate signal renders the second FET conductive, if the i-th column is not in conductive connection with the (i+1)-th input.

Memory circuit

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Poughkeepsie, NY, United States of America

Yuen H Chan