Foundry Networks, Inc.

Brocade Communications Systems, Inc.

Brocade Communication Systems LLC

Yuen Fai Wong

Yu-Mei Lin

Andrew Zhenwen Chang

Ronak Patel

Ming G Wong

Hui Zhang

Pedman Moobed

Richard Grenier

Mitri Halabi

Deepak Bansal

Robert Colvin

Frank S Yang

Vahid Naraghi

Ivy Pei-Shan Hsu

Lok Yan Hui

Daniel Sangyoung Lee

The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

System and method for high speed packet transmission

A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.

Method and apparatus for aggregating input data streams

One embodiment provides a system that performs in-order traffic aggregation from a number of low-speed ports to a high-speed port. During operation, the system receives at a low-speed port a packet, stores it in a store-and-forward FIFO associated with the low-speed port, extracts a sequence number associated with the stored packet, and stores the extracted sequence number in a sequence-number FIFO associated with the low-speed port. The system further generates an expected sequence number, which maintains a linear order with respect to sequence numbers associated with previously forwarded packets, and determines whether a front end of the sequence-number FIFO matches the expected sequence number. If so, the system removes the front end of the sequence-number FIFO buffer, retrieves a packet associated with it, forwards the retrieved packet on the high-speed port, and updates the expected sequence number by adding 1 to the packet number of the retrieved packet.

In-order traffic aggregation with reduced buffer usage

Techniques that assist in processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. In one embodiment, only a subset of FDP packets received by the network device is forwarded to the CPU for processing, the other FDP packets are dropped and not forwarded to the CPU. In this manner, the amount of processing that a CPU of the network device has to perform for incoming FDP packets is reduced. This enables the network device to support newer FDPs with shorter periodic interval requirements.

Techniques for processing incoming failure detection protocol packets

A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

Backplane interface adapter with error control and redundant fabric

Congestion control techniques based upon resource utilization information stored by a network device. According to an embodiment of the present invention, a network device is configured to identify a data source causing congestion based upon information stored by the network device identifying a set of data sources, and for each data source, information identifying the amount of a resource of the network device being used for processing data received by the network device from the data source.

Source-based congestion detection and control

A system and method for reducing the number of cycles used in CAM lookup. A network comprises a plurality of network devices connected to a router. The router comprises a media access controller which is effective to receive an input packet and a packet processor which is effective to receive the input packet from the media access controller and to extract data stored in the input packet. The router further comprises a CAM which is effective to receive the data stored in the input packet from the packet processor, a PRAM, a control processor and a bus. The control processor controls the packet processor and the CAM so that the packet processor extracts a destination address from the input packet and forwards the destination address to the CAM. The packet processor extracts a source address from the input packet and forwards the source address to the CAM. The CAM performs a lookup of the destination and source addresses in parallel. The packet processor extracts miscellaneous information, a source protocol address, and a destination protocol address from the received packet and the CAM performs a lookup of the miscellaneous information, the source protocol address, and the destination protocol address at the same time.

System and method for optimizing router lookup

Techniques for incrementing counters in an efficient manner. In one set of embodiments, counter logic circuits are provided that can operate at higher frequencies than existing counter logic circuits, while being capable of being implemented in currently available field programmable gate arrays (FPGAs) or fabricated using currently available process technologies. The counter logic circuits of the present invention may be used to increment statistics counters in network devices that support line speeds of 40 Gbps, 100 Gbps, and greater.

High speed counter design

Techniques that offer enhanced diversity in the selection of paths (e.g., ECMP paths) and/or ports from ports associated with trunks for forwarding data traffic. In one embodiment, one or more functions are used to generate a result. A first portion of the generated result may be used as an index (e.g., ECMP index) for selecting a path (e.g., an ECMP path) from multiple possible paths for forwarding a packet. A second portion of the generated result, different from the first portion, may be used as an index (trunk index) for selecting an output port from multiple output ports associated with a trunk for forwarding a packet. In this manner, selected portions of the generated result may be used as indices, one for selecting a path and another for selecting a trunk port for forwarding packets such that the two indices are not the same and are not dependent upon one another.

Growing community of inventors

San Jose, CA, United States of America

Yuen Fai Wong