Intel Corporation

Yueming Jiang

Michael W Altmann

Ravindran Mohanavelu

Su Wei Lim

Ronald W Swartz

Bruce A Tennant

Poh Thiam Teoh

Hooi Kar Loo

Jennifer Chin

Yick Yaw Ho

Hui Shi

Athourina Gevergiz

Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.

Link equalization mechanism

Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.

Apparatus, system, and method for timing recovery

Described herein are a method, an apparatus, and a system to compensate inter-symbol interference (ISI) for a signal at a receiver. The apparatus comprises a first logic unit to generate decision feedback equalizer (DFE) coefficients for data samples of a data signal; a second logic unit to generate DFE coefficients for edge samples of the data signal, wherein the DFE coefficients for the edge samples of the data signal are based at least in part on the DFE coefficients for the data samples of the data signal; and a third logic unit to compensate the data and edge samples of the data signal for inter-symbol interference at the data and edge samples of the data signal, wherein the third logic unit to compensate for inter-symbol interference by using the DFE coefficients for the data and edge samples generated by the first and the second logic units respectively.

Method, apparatus, and system to compensate inter-symbol interference

Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed.

Duty cycle calibration for receiver clock

Integrated circuits include clock deskew circuitry. The clock deskew circuitry, at the receiver side, receives data signals and a forwarded clock signal from a transmitter. The receiver detects a clock drift in a receiver clock tree, and transmits the detected clock drift to the transmitter. Based on the detected clock drift, the transmitter adjusts the timing of the transmitted signals so that the center of the data eye is aligned with the clock edge at the output of the receiver clock tree.

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Rancho Cordova, CA, United States of America

Yueming Jiang