Ningbo University

Wenzhou University

Yuejun Zhang

Pengjun Wang

Huihong Zhang

Gang Li

Bo Chen

Xiaotian Zhang

Haizhen Yu

Yunfei Yu

Keji Zhou

Zhidi Jiang

Haiming Zhang

Xuelong Zhang

Daohui Gong

Weiwei Chen

Yaopeng Kang

Xuesong Zheng

Hongzhen Fang

Jiana Lian

Jianrui Li

Shunxin Ye

Liwei Li

A control flow attacks based on return address signatures comprises: using a return address as a push return address when a response is given to an interrupt service routine; generating an encrypted push return address by an XOR encryption circuit by means of an n-bit binary key generated by a pseudo random number generator; then, generating a push_address signature value by an MD algorithm signature circuit; when the response to the interrupt service routine is over, reading an n-bit binary address out of a stack to serve as a pop return address; generating an encrypted pop return address by the XOR encryption circuit; generating a pop address signature value by the MD algorithm signature circuit; comparing the push_address signature value with the pop address signature value; and determining whether or not a data processor is under a control flow attack according to a comparison result.

Detection method of control flow attacks based on return address signatures

The disclosure discloses a method for defending control flow attacks. When a data processor gives a response to an interrupt routine, a return address and a binary key are input to an encryption circuit to be encrypted to obtain an encrypted return address, and the obtained encrypted return address is synchronously written into a stack of the data processor and an built-in register bank; when the response given to the interrupt routine by the data processor is finished, the encrypted return address is read from the tack of the data processor and the built-in register bank; afterwards, the two encrypted return addresses are decrypted by first and second decryption circuits respectively to obtain two decrypted return addresses; and the two decrypted return addresses are compared to draw a conclusion whether the data process suffers from a control flow attack, and data processor determines to continue or terminate the routine accordingly.

Method for defending control flow attacks based on XOR gates

The invention discloses a circuit aging detection sensor based on voltage comparison. A control circuit generates an aging voltage signal, a standard voltage signal and a reference voltage signal. The aging voltage signal passes through a first voltage-controlled oscillator to generate an aging frequency signal. The standard voltage signal passes through a second voltage-controlled oscillator to generate a standard frequency signal. The standard frequency signal and the aging frequency signal pass through an aging detection circuit to generate a frequency difference signal. A level signal generated by a serial data detector passes through a beat-frequency oscillator to generate a reset signal. A counter quantizes aging information, which is converted by a digital-analog converter into a quantized voltage signal. The quantized voltage signal is compared with the reference voltage signal by a voltage comparator, to generate a hopping signal at a voltage superposition node, and an aging signal is output.

Circuit aging detection sensor based on voltage comparison

A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

Domino full adder based on delayed gating positive feedback

The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter.

Circuit aging detection sensor based on lookup table

A positive feedback XOR/XNOR gate and a low-delay hybrid logic adder are provided. The low-delay hybrid logic adder comprises the positive feedback XOR/XNOR gate and an output circuit. The positive feedback XOR/XNOR gate comprises a first PMOS transistor and a second PMOS transistor used as pass transistors, a first NMOS transistor and a second NMOS transistor constituting a pull-down network, and a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor constituting a positive feedback loop. When an XOR logic output terminal of the positive feedback XOR/XNOR gate is pulled down below a switching threshold of an inverter formed by the third PMOS transistor and the fourth NMOS transistor, the positive feedback loop starts to operate to enable the XOR logic output terminal of the positive feedback XOR/XNOR gate to enter a pull-down phase to be pulled down to a low level to avoid threshold voltage losses.

Positive feedback XOR/XNOR gate and low-delay hybrid logic adder

A carbon nanotube ternary SRAM cell with an improved stability and low standby power comprises a write bit line, a read bit line, a column select bit line, an inverted column select bit line, a write word line, an inverted write word line, a read word line, an inverted read word line, a first P-type CNFET, a second P-type CNFET, a third P-type CNFET, a fourth P-type CNFET, a fifth P-type CNFET, a sixth P-type CNFET, a seventh P-type CNFET, an eighth P-type CNFET, a ninth P-type CNFET, a first N-type CNFET, a second N-type CNFET, a third N-type CNFET, a fourth N-type CNFET, a fifth N-type CNFET, a sixth N-type CNFET, a seventh CNFET, an eighth N-type CNFET and a ninth N-type CNFET. The carbon nanotube ternary SRAM cell has the advantages of being lower in power consumption, capable of solving the half-select problem and the read-disturb problem and high in static noise margin.

Carbon nanotube ternary SRAM cell with improved stability and low standby power

A data selector based on TVD includes two AND gates, an OR gate, and three buffers, wherein the two AND gates and the OR gate adopt a three-phase dual-track pre-charge logic as a work logic. The data selector fulfills one time of evaluation operation and has three stages in one cycle. When a discharge control signal and a pre-charge control signal are at low levels, the data selector enters a pre-charge stage. When an evaluation signal is changed to a high level from a low level, the data selector implements the evaluation operation to fulfill the circuit function. When the discharge control signal is changed to a high level from the low level, the data selector enters a discharge state and gets ready for the next evaluation operation.

Data selector based on threshold voltage defined

A multi-port PUF circuit based on MOSFET current division deviations comprises a reference source, a row decoder, a column decoder, a timing controller and 32 PUF arrays. Each PUF array comprises 512 PUF cells arranged in 128 rows and 4 columns, an arbiter, a 1inverter, a 2inverter, a 3inverter, a 4inverter and eight transmission gates. The reference source is connected to the PUF arrays. The moutput terminal of the row decoder is connected to the mrow selective signal input terminals of the 32 PUF arrays. The joutput terminal of the column decoder is connected to the jselective signal input terminals of the 32 PUF arrays. The 1output terminal of the timing controller is connected to the control terminal of the row decoder. The 2output terminal of the timing controller is connected to the control terminal of the column decoder. The multi-port PUF circuit has the advantages of small circuit area and low power consumption while ensuring circuit performance.

Multi-port PUF circuit based on MOSFET current division deviations

A metastable true random number generator realized on an FPGA comprises a configurable delay chain including rough adjustment module and a fine adjustment module. The rough adjustment module comprises 32 rough adjustment cells each including a 16-input lookup table and a two-to-one selector. The 1input port of each 16-input lookup table is connected to the 1input terminal of the corresponding two-to-one selector, and the connecting terminal is the input terminal of the corresponding rough adjustment cell. The 2input port, the 3input port, the 4input port, the 5input port and the 6input port of each 16-input lookup table are all accessed to a low level 0. The output port of each 16-input lookup table is connected to the 2input terminal of the corresponding two-to-one selector. The metastable true random number generator has the advantages of being capable of well counteracting inherent delay deviations, high in automation degree and high in output rate and having an operating point not prone to deviation.

Metastable true random number generator realized on FPGA

Disclosed is a lightweight bistable PUF circuit, comprising a decoding circuit, a timing control circuit, a PUF cell array and n sharing foot circuits. The PUF cell array is formed by m*n PUF cells arrayed in m lines and n columns. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the four PMOS transistors have the minimum width-to-length ratio of 120 nm/60 nm under a TSMC 65 nm process. Each sharing foot circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first two-input NAND gate and a second two-input NAND gate, and the four NMOS transistors have a width-to-length ratio ranging from 2 um/60 nm to 8 um/60 nm. The lightweight bistable PUF circuit has a reset function and the advantages of small area, low power consumption, small time delay and high speed.

Lightweight bistable PUF circuit

A static memory cell capable of balancing bit line leakage currents is characterized by including a 1PMOS transistor, a 2PMOS transistor, a 1NMOS transistor, a 2NMOS transistor, a 3NMOS transistor, a 4NMOS transistor, a 5NMOS transistor, a 6NMOS transistor, a 7NMOS transistor, an 8NMOS transistor, a write word line, a read word line, a read bit line, an inverted read bit line, a write bit line and an inverted write bit line. The 1NMOS transistor, the 2NMOS transistor, the 3NMOS transistor and the 4NMOS transistor are all normal threshold NMOS transistors. The 1PMOS transistor and the 2PMOS transistor are both low threshold PMOS transistors. The 5NMOS transistor, the 6NMOS transistor, the 7NMOS transistor and the 8NMOS transistor are all low threshold NMOS transistors. The static memory cell has the advantages of high read operation speed, low power consumption and high stability under low operating voltage conditions.

Static memory cell capable of balancing bit line leakage currents

The present invention discloses a ternary 2-9 line address decoder realized by CNFET, comprising two ternary 1-3 line address decoders of the same structure, nine three-input NAND gates of the same structure and nine inverters of the same structure; the ternary 1-3 line address decoder comprises a 1CNFET transistor, a 2CNFET transistor, a 3CNFET transistor, a 4CNFET transistor, a 5CNFET transistor, a 6CNFET transistor, a 7CNFET transistor, an 8CNFET transistor, a 9CNFET transistor, a 10CNFET transistor and an 11CNFET transistor; as compared with a 3-8 line address decoder, it features in limited deviation to an output terminals and significant reduction in the number of input terminals, which can minimize the number of ports as packaging, and improve decoding efficiency; furthermore, it is realized by CNFET, which features in low power consumption and less postponement.

Ternary 2-9 line address decoder realized by CNFET

The present invention discloses a multi-port PUF circuit based on NMOS zero temperature coefficient point, comprising an input register, a deviation current source, a arbiter and a disturbing module used to construct a multi-port PUF circuit; the input register comprises m D-flip-flops; the deviation current module comprises m deviation current cells; the arbiter comprises 2n current sensitive amplifiers; the disturbing module comprises n 2-input XOR gates; wherein an input challenge used to configure deviation current generation module can update IDs without replacement of hardware. In addition, it has a capability of producing a multi-bit IDs in one clock cycle. Post-layout simulation results show that the PUF circuit is provided with excellent uniqueness and randomness with reliability up to 98.2% across temperature variation from &#x2212;40&#xb0; C. to 125&#xb0; C., and supply voltage variation from 1.08V to 1.32V; it can be applied in information security field.

Multi-port PUF circuit based on NMOS zero temperature coefficient point

The present invention discloses a static RAM for defensive differential power consumption analysis, comprising a replica bit-line circuit, a decoder, an address latch circuit, a clock circuit, n-bit memory arrays, n-bit data selectors, n-bit input circuit and n-bit output circuits; the output circuits comprises a sensitivity amplifier and a data latch circuit; the 1st PMOS tube, the 2nd PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 1st NMOS tube, the 2nd NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube constitute the sensitivity amplifier; two NOR gates, the 8th PMOS tube, the 9th PMOS tube, the 10th PMOS tube, the 11th PMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the 10th NMOS tube constitute the data latch circuit; the present invention is characterized in that energy consumption in each working cycle is basically identical, which is provided with higher capability in defense of differential power analysis.

Growing community of inventors

Zhejiang, China

Yuejun Zhang