Infinera Corporation

Yuejian Wu

Han Henry Sun

Sandy Thomson

Kuang-Tsan Wu

David J Krause

John Duncan McNicol

Stanley H Blakey

Mehdi Karimi

Scott G Pringle

Ting-Kuang Chiang

Ahmed Awadalla

Scott Pringle

Alexander Kaganov

Sofia Amado

Aroutchelvame Mayilavelane

Christopher Fludger

Consistent with the present disclosure, multiple forward error correction (FEC) encoders are provided for encoding a respective one of a plurality of data streams. A mechanism is provided to mix or interleave portions of the encoded data such that each subcarrier carries information associated with each data stream, as opposed to each subcarrier carrying information associated with only a corresponding one of the data streams. As a result, both higher SNR and low SNR optical subcarriers carry such information, such that errors occurring during transmission are distributed and not concentrated or limited to information associated with a single data stream. Accordingly, at the receive end, each FEC decoder decodes information having a similar overall error rate. By balancing the error rates across each FEC encoder/decoder pair, the overall ability to correct errors improves compared to a system in which mixing or interleaving is not carried out.

Methods and apparatus for sub-carrier interleaving to improve overall forward error correction

An optical system includes a transmitter module and/or a receiver module. The transmitter module is configured to receive input data, map the input data to a set of subcarriers associated with an optical communication channel, independently apply spectral shaping to each of the subcarriers, generate input values based on the spectral shaping of each of the subcarriers, generate voltage signals based on the input values, modulate light based on the voltage signals to generate an output optical signal that includes the subcarriers, and output the output optical signal. The receiver module is configured to receive the output optical signal, convert the output optical signal to a set of voltage signals, generate digital samples based on the set of voltage signals, independently process the digital samples for each of the subcarriers, map the processed digital samples to produce output data, and output the output data.

Channel carrying multiple digital subcarriers

A system may include an optical transmitter and an optical receiver. The optical transmitter may generate optical signals associated with sub-carriers, and may provide the optical signals via an optical link. The optical receiver may receive the optical signals via the optical link, and may generate samples based on the optical signals. The samples may be associated with the sub-carriers. The optical receiver may combine the samples to form a time domain sample vector having a particular size, and may generate a frequency domain sample vector, having the particular size, based on the time domain sample vector. The optical receiver may demultiplex the frequency domain sample vector to generate domain sample vectors corresponding to the sub-carriers. The optical receiver may process the frequency domain sample vectors to generate equalized frequency domain sample vectors, and may output the equalized frequency domain sample vectors.

Configurable frequency domain equalizer for dispersion compensation of multiple sub-carriers

An optical system includes an optical transmitter configured to modulate an optical signal to carry data, associated with an optical channel, via multiple sub-carriers in a quantity greater than four. The optical system further includes an optical receiver configured to demodulate the optical signal to recover the data from the multiple sub-carriers.

Efficient processing of high data rate signals with a configurable frequency domain equalizer

A low-density parity-check (LDPC) decoder may comprise a shift register configured to receive LDPC coded data, perform an iteration associated with decoding the LDPC coded data, and provide a result of performing the iteration. The shift register may include a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle, a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration, a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration. The quantity of stages times the quantity of lanes may be greater than the quantity of storage elements by a particular number of storage elements. The particular number of storage elements may be displaced by the set of check node elements.

Efficient storage architecture for low-density parity-check decoding

A low-density parity-check (LDPC) decoder may receive LDPC coded data. The LDPC decoder may perform a decoding iteration associated with decoding the LDPC coded data. The decoding iteration may be performed by processing a group of layers. Each layer may include a corresponding set of check node elements, and may be processed by causing each check node element, of the set of check node elements corresponding to the layer, to update a set of variable node elements, connected to the check node element and associated with the LDPC coded data, based on a check node function associated with the check node element. The decoding iteration may be performed such that each layer is processed in parallel, and such that each check node element updates the corresponding set of variable node elements in parallel. The LDPC decoder may provide a result of performing the decoding iteration.

Code design and high-throughput decoder architecture for layered decoding of a low-density parity-check code

An optical receiver may receive input signals carried by sub-carriers, and may apply test phases to each input signal. The optical receiver may determine error values, associated with test phases, for each input signal. The optical receiver may calculate updated metric values, associated with the test phases, for a particular input signal, based on a first error value and a second error value. The first error value may be associated with a first sub-carrier, and the second error value may be associated with a second sub-carrier. The optical receiver may compare the updated metric values associated with the particular input signal, and may determine a test phase that represents an estimated phase, associated with the particular input signal, based on the comparison. The optical receiver may determine a phase estimate value based on the test phase, and may provide the phase estimate value to modify the particular input signal.

Estimating phase using test phases and interpolation for modulation formats using multiple sub-carriers

An optical receiver may receive input signals carried by respective sub-carriers. The optical receiver may determine, based on the input signals, a compensation value to be used to modify an input signal. The optical receiver may use the compensation value to adjust the input signal to form a modified input signal. The compensation value may be used to modify a frequency or a phase of the input signal. The optical receiver may determine, based on the modified input signal, a phase estimate value that represents an estimated phase associated with the input signal. The optical receiver may combine the compensation value and the phase estimate value to form a phase adjustment signal, may combine the input signal and the phase adjustment signal to form an output signal, and may output the output signal.

Frequency and phase compensation for modulation formats using multiple sub-carriers

In one implementation, a device may include a voltage regulator circuit, a data processing circuit, and an error correction circuit, where the error correction circuit may correct errors in data processed by the data processing circuit to obtain error-corrected data and output an error-corrected version of the processed data. Additionally, an error monitor circuit may output an error signal indicative of a level of the errors in the processed data. A control circuit may receive the error signal and control the voltage regulator circuit to adjust, based on the error signal, the supply voltage to the data processing circuit. In some implementations, the control circuit may also base its decision to control the voltage regulator circuit based on available timing margins in the data processing circuit.

Adaptive voltage scaling based on the results of forward error correction processing

A system is to receive a word on which to perform error correction; obtain segments, from the word, each segment including a respective subset of samples; update, on a per segment basis, the word based on extrinsic information associated with a previous word; identify sets of least reliable positions (LRPs) associated with the segments; create a subset of LRPs based on a subset of samples within the sets of LRPs; generate candidate words based on the subset of LRPs; identify errors within the word or the candidate words; update, using the extrinsic information, a segment of the word that includes an error; determine distances between the candidate words and the updated word that includes the updated segment; identify best words associated with shortest distances; and perform error correction, on a next word, using other extrinsic information that is based on the best words.

Iterative forward error correction (FEC) on segmented words using a soft-metric arithmetic scheme

A system is configured to receive a block of symbols, associated with a phase-modulated signal that includes data symbols that correspond to a payload associated with the signal, and control symbols; process the control symbols to identify an amount of phase noise associated with the control symbols; reset a phase, associated with each of the data symbols, based on the amount of phase noise and a reference phase; interleave the respective data samples, of each of the data symbols with other data samples, where the interleaved respective data samples cause errors, associated with the respective data samples, to be spread out among the other data samples and reduces an error rate relative to a prior data rate that existed before the interleaving; and perform forward error correction on the interleaved respective data samples.

Coherent detection using coherent decoding and interleaving

A system is configured to receive a word that includes a group of samples; randomly select a subset of the samples; identify first samples, from the subset, with a lowest level of reliability; select another subset of the samples; identify second samples, from the other subset, with a lowest level of reliability; and create a merged subset based on selected first samples and selected second samples. The system is also configured to select a further subset of the samples; identify third samples, from the further subset, with a lowest level of reliability; identify fourth samples, from the merged subset, associated with a lowest level of reliability; create another merged subset based on a greater probability that fourth samples than third samples are included in the other merged subset; and generate another word based a sample from the other merged subset; and process the word using the other word.

Reducing processing bias in a soft forward error correction (FEC) decoder

A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.

Method, system, and apparatus for interpolating an output of an analog-to-digital converter

Filter implementation using Hermitian conjugates and time division multiplexing (TDM) is disclosed to more efficiently compensate for chromatic dispersion of optical signals transmitted over a fiber optic medium. Embodiments for an input, filter, and output sections of a Digital Signal Processor (DSP) are described. The disclosed methods, and corresponding apparatus and systems enables a substantial reduction in the complexity of the hardware needed to implement CD compensation in the DSP. According to another embodiment, Inverse-Fourier transform circuits receive TDM data from the filter section and assemble the TDM data format back to a non-TDM format.

Growing community of inventors

Woodlawn, Canada

Yuejian Wu