Taiwan Semiconductor Manufacturing Comp. Ltd.

Yueh-Yi Chen

Tseng Chin Lo

Bo-Sen Chang

Chih-Ting Sun

Kung-Cheng Lin

Ying-Jung Chen

Meng Lin Chang

Hsin-Che Chiang

Shih-Hsun Chang

Shu-Hui Wang

Ju-Li Huang

Ju-Yuan Tzeng

Wei-Ze Xu

Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.

Method of measuring mask overlay using test patterns

Integrated circuit overlay test patterns and method thereof

A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Methods of forming metal gates

Growing community of inventors

Hsinchu, Taiwan

Yueh-Yi Chen