M31 Technology Corporation

Yueh-Chuan Lu

Ching-Hsiang Chang

Yuan-Hsun Chang

Huai-Te Wang

Pin-Hao Feng

An integrated circuit in a transmitter includes a multi-lane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi-lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively. (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier.

Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver

An integrated circuit in a physical layer of a receiver is provided. The integrated circuit includes a multi-lane interface, a lane selection circuit and N sampling circuits. The multi-lane interface has N lanes. N is an integer greater than one. The lane selection circuit, coupled to the multi-lane interface, is configured to select M of the N lanes as M clock lanes, and output M signals on the M clock lanes respectively. M is a positive integer less than N. Remaining (N&#x2212;M) lanes serve as (N&#x2212;M) data lanes. The N sampling circuits are coupled to the multi-lane interface and the lane selection circuit. (N&#x2212;M) of the N sampling circuits are coupled to the (N&#x2212;M) data lanes respectively. Each of the (N&#x2212;M) sampling circuits is configured to sample a signal on one of the (N&#x2212;M) data lanes according to one of the M signals on the M clock lanes.

A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops.

Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof

A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.

Physical layer circuitry for multi-wire interface

An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes; a second layer of clock lane selection units arranged to select the one or two selected lanes as one or two clock lane and output signals on the one or two selected clock lane; and a plurality of sampling units, each coupled to second layer of clock lane selection units, each arranged to sample one of the first and second lanes according to the signal on the selected clock lane.

Integrated circuits adaptable to interchange between clock and data lanes for use in clock forward interface receiver

The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).

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Taipei, Taiwan

Yueh-Chuan Lu