Taiwan Semiconductor Manufacturing Comp. Ltd.

National Cheng-kung University

Yueh-Chieh Chu

Yun-Chi Wu

Tsung-Yu Yang

Chung-Jen Huang

Cheng-Bo Shu

Jui-Yu Pan

Jing-Ru Lin

Yonhua Tzeng

Chun-Cheng Chang

Pin-Yi Li

Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Integrated chip including a tunnel dielectric layer which has different thicknesses over a protrusion region of a substrate

Embedded flash memory cell including a tunnel dielectric layer having different thicknesses over a memory region

The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

Integrated chip having a logic gate electrode and a tunnel dielectric layer

Method to fabricate uniform tunneling dielectric of embedded flash memory cell

A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.

Method for manufacturing memory device and method for manufacturing shallow trench isolation

A graphene optoelectronic detector is disclosed, which comprises: an insulating substrate with a graphene layer disposed thereon; a first electrode disposed on the graphene layer or between the graphene layer and the insulating substrate; and a second electrode disposed on the graphene layer or between the graphene layer and the insulating substrate, wherein there is a predetermined distance between the first electrode and the second electrode, and the first electrode and the second electrode are at different electrical potentials, wherein a high-drift carrier moving region is disposed between the first electrode and the second electrode, and a low-drift carrier moving region is disposed outside the high-drift carrier moving region. In addition, the present invention further provides a method for detecting photons and electromagnetic energy using the aforementioned graphene detector.

Graphene optoelectronic detector and method for detecting photonic and electromagnetic energy by using the same

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Tainan, Taiwan

Yueh-Chieh Chu