Taiwan Semiconductor Manufacturing Comp. Ltd.

Yueh Chiang

Shang-Hsuan Chiu

Hidehiro Fujiwara

Wei-Chang Zhao

Yi-Hsin Nien

Guang-Cheng Wang

Kuang-Ching Chang

Kinshuk Khare

Ming-Xiang Liu

Ming-Xiang Lu

Yu Jung Li

A circuit includes a first Dual Interlocked Storage Cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component operatively coupled to one another as a loop. The first and second DICE components form a first sub-latch configured to receive an input signal, the third and fourth DICE components form a second sub-latch configured to receive the same input signal, the first sub-latch is configured to provide, at a first node, an intermediate signal based on the input signal, and the second sub-latch is configured to provide, at a second node, the same intermediate signal based on the input signal. The circuit includes a first inverter configured to logically invert the intermediate signal and provide, at a third node, an output signal. The circuit includes a second inverter configured to logically invert the intermediate signal and provide, at the third node, the output signal.

Latch circuits and methods for operating the same

A flip-flop includes a first input circuit, a first NOR logic gate, a stacked gate circuit, a first NAND logic gate and an output circuit. The first input circuit generates a first signal responsive to at least a first data signal, a first or a second clock signal. The first NOR logic gate is coupled between a first and a second node, and generates a second signal responsive to the first signal and a first reset signal. The stacked gate circuit is coupled between the first and a third node, and generates a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and a fourth node, and generates a fourth signal responsive to the third signal and a second reset signal. The output circuit is coupled to the fourth node, and generates a first output signal responsive to the fourth signal.

Integrated circuit and method of forming the same

A flip-flop includes a first set of transistors of a first type being located in a first row and a second set of transistors of a second type being located in a second row. The second type being different from the first type. The first and second set of transistors include a first master latch circuit and a second master latch circuit. The first and second master latch circuit are separated from each other in the first direction by a first distance. A first output signal of the first and second master latch circuit is a first input signal of the first master latch circuit and the second master latch circuit. A second output signal of the first and second master latch circuit is a second input signal of the first and second master latch circuit.

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Hsinchu, Taiwan

Yueh Chiang