Sifive, Inc.

Yueh Chi Wu

Nicolas Rémi Brunie

Yohann Rabefarihy

Apparatus and methods for tracking sub-micro-operations and groups thereof are described. An integrated circuit includes a load store unit configured to receive store micro-operations cracked from a vector store instruction. The load store unit is configured to unroll multiple store sub-micro-operations from each of the store micro-operations. The load store unit includes an issue status vector to track issuance of each sub-micro-operation, an unroll status vector to track unrolling of each sub-micro-operation associated with a group of sub-micro-operations, and a replay status vector to track a replayability of sub-micro-operations associated with the group of sub-micro-operations.

Tracking of store operations

A method for executing vector iota (viota) operation is disclosed. The method includes fetching a viota instruction, decoding the viota instruction into multiple viota micro-operations (uops), computing a first element viota value of a respective viota uop, determining a respective last element viota value of the respective viota uop based on the first element viota value of the respective uop, and writing the respective last element viota value of the respective viota uop to an allocated physical register. Each viota uop of the multiple viota uops has multiple elements, and each element has a viota value corresponding to a sum of active mask bits of preceding elements of the viota uops. The multiple elements of each viota uop comprise at least a first element that has a starting bit position of a respective uop and a last element that has an ending bit position of the respective uop.

Out-of-order vector iota calculations

Apparatus and methods for processing of a vector load or store micro-operation with mask information as a no-operation (no-op) when a mask vector for the vector load or store micro-operation has all inactive mask elements or processing vector load or store sub-micro-operation(s) with active mask element(s) are described. An integrated circuit includes a load store unit configured to receive load or store micro-operations cracked from a vector load or store operation, determine that a mask vector for the vector load or store micro-operation is fully inactive, and process the vector load or store micro-operation as a no-operation. If the mask vector is not fully inactive, the vector load or store micro-operation is unrolled into vector load or store sub-micro-operation(s) which have active mask element(s). Vector load or store sub-micro-operation(s) which have inactive mask element(s) are ignored.

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Taichung, Taiwan

Yueh Chi Wu