Realtek Semiconductor Inc.

Yuefeng Chen

Chen-Tung Lin

Xuanming Liu

Hui Gu

A method of defense against cryptosystem timing attack such as Rivest-Shamir-Adleman (RSA) cryptosystem timing attack, an associated cryptosystem processing circuit and an associated electronic device are provided. The method may include: utilizing a point double calculation circuit to perform a plurality of point double calculation operations related to a predetermined cryptosystem; utilizing a point add calculation circuit to perform a plurality of point add calculation operations related to the predetermined cryptosystem; and in response to there being no need to perform any point add calculation operation related to the predetermined cryptosystem, utilizing a dummy point add calculation circuit to perform a dummy point add calculation operation to emulate a calculation time of performing the any point add calculation operation, without changing a calculation result before performing the dummy point add calculation operation.

Method of defense against cryptosystem timing attack, associated cryptosystem processing circuit, and associated electronic device

A method for performing a power disturbing operation to reduce a success rate of cryptosystem power analysis attack, an associated cryptosystem processing circuit and an associated electronic device are provided. The method includes: generate at least one random number; generating a plurality of power disturbing parameters respectively corresponding to a plurality of bit calculation phases according to the at least one random number, where the plurality of bit calculation phases represent a plurality of cryptosystem processing phases related to a predetermined cryptosystem, and correspond to a plurality of private key bits of a private key, respectively; and according to the plurality of power disturbing parameters, enabling at least one predetermined circuit of a plurality of predetermined circuits in the plurality of bit calculation phases, respectively, to use power corresponding to the plurality of power disturbing parameters to perform the power disturbing operation in the plurality of bit calculation phases, respectively.

Method for performing power disturbing operation to reduce success rate of cryptosystem power analysis attack, cryptosystem processing circuit, and electronic device

A processing device includes: a receiving module for receiving a configuration from a control device, wherein the configuration includes a destination address, a length, a filled value and a function type; a control module for (A) configuring an access state for accessing a slave device according to the function type and (B) comparing a counting value with the length to generate a comparison result according to the function type, determining whether data received from the slave device reaches an end to generate a determination result, or both; a reading module for reading the data according to the access state; a writing module for writing the filled value to the destination address according to information of the access state, the determination result and the comparison result; and a transmitting module for transmitting an interrupt signal to the control device according to result(s) of the determination result and the comparison result.

Device and method for handling programming language function

A joint test action group transmission system includes a host terminal and a slave terminal. The slave terminal includes a test access port (TAP) circuit, an internal memory, and a memory interface controller. The TAP circuit includes a test data register set. The memory interface controller stores the data received from the TAP circuit to the internal memory. The host terminal transmits a set of download instruction bits to the TAP circuit to have the TAP circuit select the test data register set, and have the TAP circuit enter a data shift status to receive a data package through the test data register set. During the process of receiving the data package, the TAP circuit remains in the data shift status to receive the address and at least one piece of data stored in the data package continuously.

Joint test action group transmission system capable of transmitting data continuously

A method for controlling operations of an asynchronous FIFO memory includes: determining a current depth of the asynchronous FIFO memory according to at least one of a clock ratio, a burst length and a continuous transmission length, where the clock ratio is a ratio of a frequency of a first clock signal used by a master device to a frequency of a second clock signal used by a slave device; configuring one or more entries of the asynchronous FIFO memory to be used according to the current depth; and controlling a plurality of FIFO clock signals provided to the asynchronous FIFO memory according to the current depth. One FIFO clock signal corresponds to one entry, and one or more FIFO clock signals corresponding to one or more entries that are not configured according to the current depth are disabled.

Methods for controlling asynchronous FIFO memory and data transmission system utilizing the same

A processing device used in a bus, for executing a programming language function of a central processing unit (CPU), comprises a receiving circuit, for receiving a joint command from the CPU, to assist the CPU to execute the programming language function, wherein the joint command comprises an extended read command and an extended write command; a transmitting circuit, coupled to the receiving circuit, for transmitting the extended read command to a slave device, to receive a first response message via the receiving circuit in response to the extended read command from the slave device, wherein the first response message comprises at least one data read by the slave device from a memory block; and a writing circuit, coupled to the receiving circuit and transmitting circuit, for writing the at least one data into a destination address corresponding to the programming language function according to the extended write command.

A data storage system includes a first memory, a second memory, and a memory controller. The memory controller transmits a first data segment from the first memory to the second memory according to an initial address, adds a first interval value to the initial address to generate a succeeding address, and updates a stream number. When the stream number has not reached a target stream number, the memory controller transmits second data segment from the first memory to the second memory according to the succeeding address, and updates the stream number. When the stream number has reached the target stream number, the memory controller sets the stream number to an initial value, adds an offset value to the initial address to update the succeeding address, and transmits a third data segment from the first memory to the second memory according to the updated succeeding address.

Data storage system capable of performing interleaving scatter transmissions or interleaving gather transmissions

A data transmission system includes a first memory, a second memory, a third memory; and a memory controller. The memory controller includes a first channel control module and a second channel control module. The first channel control module is coupled to the first memory and the second memory. The first channel control module transmits a first set of data between the first memory and the second memory, and transmits a switch signal after the first set of data is transmitted. The second channel control module is coupled to the first channel control module, the first memory, and the third memory. The second channel control module transmits a second set of data between the first memory and the third memory after receiving the switch signal.

Data transmission system capable of perform union task with a plurality of channel control modules

A JTAG TAP apparatus coupled between a host and an interface circuit, which is coupled between a memory and the JTAG TAP apparatus, includes first pin, second pin, first data register, and second data register. The first data register stores data shifted in by the host via the first pin, the shifted in data is stored into a specific address of the memory via the interface circuit. The second data register stores read back data from the specific address of the memory via the interface circuit and outputs the read back data to the host via the second pin to make the host compare the shifted in data with the read back data to perform comparison test.

Scheme applied in JTAG TAP apparatus, JTAG host, and target system capable of achieving data verification as well as saving on-chip circuit costs

A data transmission system includes a host, a universal serial bus (USB) interface adaptor, a first-in first-out (FIFO) interface adaptor, a plurality of functional circuits, and a bus bridge circuit. The host accesses data according to the communications protocols of USB. The USB interface adaptor accesses data through a first port according to the communications protocols of USB, and accesses data through a second port according to the communications protocols of FIFO. The FIFO interface adaptor accesses data through a third port coupled to the second port according to the communications protocols of FIFO, and accesses data through a fourth port according to the communications protocols of a specific type of bus. The bus bridge circuit transmits the data received from the fourth port to a functional circuit according to the communications protocols of the specific type of bus.

Data transmission system capable of transmitting a great amount of data

A test access port circuit includes a data input terminal, a reset terminal, a mode selection terminal, at least one test data register set, an auxiliary data register set, an instruction register set, and a controller. The controller is coupled to the mode selection terminal and the instruction register set, and controls the at least one test data register set, the auxiliary data register set, and the instruction register set according to at least mode selection signal received by the mode selection terminal. In a reset terminal input mode, when the controller controls a test data register set of the at least one test data register set to store a first input data bit received by the data input terminal, the auxiliary data register set stores a second input data bit received by the reset terminal.

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Suzhou, China

Yuefeng Chen