Netlogic Microsystems, Inc

Sun Mirosystems, Inc.

Yuefei Ge

Michael E Ichiriu

Anup S Tirumala

Lan Lee

Masaru Shinohara

David M Pini

A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and generating a sign bit from the part of the data. The sign bit is transferred to the aligner along the bypass, and the data is separately transferred to the aligner along a data path.

Sign generation bypass path to aligner for reducing signed data load latency

A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.

Row redundancy in a content addressable memory device

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San Jose, CA, United States of America

Yuefei Ge