Cadence Design Systems, Inc.

Yue-Zhong Shu

Chi-Yuan Lo

Parveen Khurana

Shun-Lin Su

Nandu Kumar Chowdhury

Yoshimi Kitagawa

Disclosed herein are embodiments of systems, methods, and products to automatically and intelligently generate a test bench to test an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) design. A computer may receive netlist of the IC design forming a device under test (DUT). From the DUT, the computer may extract and/or calculate one or more parameters. Based on the one or more parameters, the computer may generate a test bench comprising a resistance inductance capacitance (RLC) circuit to provide ESD stimulus to the DUT. The ESD stimulus and therefore the test bench may be based on a human body model (HBD) or a charged device model (CDM). In case of the CDM, the computer may allow a circuit designer to select or deselect package parameters for testing the ESD protection circuit.

Systems and methods to generate a test bench for electrostatic discharge analysis of an integrated circuit design

Using an adaptive square mesh for parasitic extraction, small squares of a predetermined minimum size will be placed where accuracy in the parasitic calculations is most critical&#x2014;around edges, contacts and vias, and corners. Then, in areas where the parasitic analysis is less critical, for example in open spaces, a more coarse grid consisting of larger squares may be used to calculate the parasitic values in those spaces. Squares in the mesh may increase in size gradually to provide more accurate results.

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Shanghai, China

Yue-Zhong Shu