Emc IP Holding Company LLC

Emc Corporation

Other

Shanghai Jiaotong University

China Flash Co., Ltd.

Successfactors, Inc.

Memverge, Inc.

Anovent Pharmaceutical (u.s.), LLC

Shanghai Geometrical Perception and Learning Co., Ltd.

Shanghai Superconductor Technology Co., Ltd.

Supermag Technology (shanghai) Ltd.

Supermag Technology (shanghai) Co., Ltd.

Yue Zhao

Peiyu Zhuang

Yue Li

Jie Yu

Wei Wu

Yuanjie Wu

Wei Kang

Arun Joseph

Minjie Zhang

Zhijian Jin

James Odis Pendergraft

Hong Nie

Norman Speciner

Yue Wu

Chunsheng Cheng

Jeegn Chen

Chunjiang Guo

Jiamin Zhu

Guangyu Jiang

Robert W Beauchamp

Ning Xu

Kunwu Huang

Haiyan Wang

Ying Xu

Ying Sun

Cai Gu Huang

Sikan Chen

Songhua Shi

Dan Xue

Zeyu Zhu

Yijun Ding

Mingyu Zhou

Xiaozhi Yan

Dahuai Wang

Jingyuan Chu

Hui Yuan

Donghong Wu

A preparation device for an alloy target includes a material nozzle, a high-energy laser, and a target support substrate, the material nozzle and the high-energy laser are respectively arranged above the target support substrate. The preparation device uses the material nozzle to spray the material powder required for the alloy target to be prepared, the injection efficiency is independently adjusted to achieve the purpose of non-fixed composition of the alloy target, and the spatial position and angle of the material nozzle are independently adjusted to ensure uniform composition and density of the target, the high-energy laser beam generated by the high-energy laser is used to heat the material powder in the spraying area to form a target coating of the required composition, the target support substrate is used to support the target coating formed by the material powder.

Preparation device and preparation method for alloy targets

A method for fabricating a lamination structure of a second-generation high-temperature superconducting (2G-HTS) tape is provided. Suitable lamination tapes are selected and subjected to local oxidation on side to form a locally oxidized region having a target pattern. The lamination tapes and a to-be-laminated 2G-HTS tape are sequentially arranged, where the locally-oxidized side of each of the lamination tapes faces toward the 2G-HTS tape. The lamination tapes and the to-be-laminated 2G-HTS tape are simultaneously immersed in a molten solder pool, and subjected to reel-to-reel squeezing lamination to form the desired lamination structure. A lamination structure fabricated by the method is also provided.

Lamination structure of second generation high-temperature superconducting (2G-HTS) tape and method for fabricating the same

A method of sparse array oriented approach for DOA estimation of grating lobe target filtering includes sub-array division processing of received echoes in multiple channels; digital beamforming is performed on each sub-array obtained after division to realize DOA estimation; the echo power of the beam pointing at each angle is calculated and the peak point is detected; peak threshold discrimination processing is performed based on the determined peak threshold; if the current sub-array satisfies the identified peak threshold, the corresponding power spectrum extreme is calculated to obtain the final DOA estimation. The present invention also relates to a corresponding device, processor and computer-readable storage medium thereof. With the use of this sparse array oriented method, device, processor and computer-readable storage medium for implementing filtered DOA estimation of a gate lobe target, the interference of the gate target is effectively avoided by dividing the subarray and binarizing the angular power spectrum.

Method of sparse array oriented approach for DOA estimation of grating lobe target filtering

A second-generation high temperature superconducting (HTS) strip and a preparation method thereof are provided. The second-generation HTS strip includes a superconducting strip body and a stabilizing layer arranged thereon. The stabilizing layer is a copper-graphene composite film with a total thickness of 2-30 microns on one side. The superconducting strip may be obtained by the preparation method of: (1) putting a superconducting strip body into a magnetron sputtering reaction chamber, followed by pumping to a high-level vacuum and filling with a working gas; (2) using copper and graphene as targets, and performing a sputter coating by controlling a magnetron sputtering power, to deposit the targets onto at least one surface of the superconducting strip body. The prepared HTS strips containing copper-graphene stabilizing layer with high strength and high conductivity may have 30%-70% higher tensile strength than conventional copper plated superconducting strips, with less than 10% IACS attenuation in conductivity.

Second-generation HTS strip and preparation method thereof

A method for fabricating a second generation high-temperature superconductor (2G-HTS) tape, including: (S1) depositing a superconducting thin film on a surface of a ductile metal substrate with a buffer layer; (S2) forming a micro-holes array pattern on a surface of the superconducting thin film by etching using a reel-to-reel dynamic femtosecond infrared laser etching system, where the micro-holes array pattern covers the superconducting thin film; (S3) depositing a superconducting thick film on the surface of the superconducting thin film; and (S4) depositing a silver protective layer and a copper stabilization layer on a surface of the superconducting thick film.

Second generation high-temperature superconducting (2G-HTS) tape and fabrication method thereof

The present invention relates to a liquid, propellant-free pharmaceutical preparation and a method for administering a pharmaceutical preparation by nebulizing the pharmaceutical preparation in an inhaler. The propellant-free pharmaceutical preparation comprises: (a) an active substance selected from umeclidinium bromide and vilanterol trifenatate and combinations thereof; (b) a solvent; (c) a pharmacologically acceptable solubilizing agent; and (d) a pharmacologically acceptable preservative, and optionally includes a pharmacologically acceptable stabilizer, a pharmacologically acceptable co-solvent, or other pharmacologically acceptable additives.

Inhalable formulation of a solution containing vilanterol trifenatate and umeclidinium bromide

A method for improving current carrying capacity of a second-generation high-temperature superconducting tape, which includes: stretching the second-generation high-temperature superconducting tape in a high-temperature environment, and carrying out an oxygenation heat treatment on the stretched second-generation high-temperature superconducting tape The atmosphere of the high-temperature environment is oxygen, or an inert gas, or a mixture thereof, and a temperature of the high-temperature environment is 450-650&#xb0; C.; and a strain for stretching ranges from 0.1% to 1%, and a time for stretching ranges from 1 minute to 100 hours. The method of the present invention is a post-processing technique for the second-generation high-temperature superconducting tape with a simple treatment process and a controllable result, and by stretching, current carrying capacity of the superconducting tape is improved and anisotropy of superconductivity is reduced.

Method for improving current carrying capacity of second-generation high-temperature superconducting tape

A word line decoding circuit and memory comprises a first address decoding module to obtain word line logic signals; a word line pre-coding module to obtain word line pre-coding signals and first switch signals; a second address decoding module to obtain first and second selection signals; a third address decoding module to obtain third selection signals; a first level conversion module which performs level conversion on the first selection signals to obtain first and second control signals; a second level conversion module which performs level conversion on the second selection signals to get third and fourth control signals; a third level conversion module which performs level conversion on the third selection signals to obtain fifth control signals; a word line toggle switch signal generation module which generates second switch signals based on each control signal; and a word line toggle module to generate word line signals.

Word line decoding circuit and memory

The present disclosure relates to a NOR flash memory circuit, a data writing method, a data reading method, and a data erasing method. The NOR flash memory circuit includes: a NOR memory array, a source voltage selection unit, a well voltage selection unit, a word line gating unit, a bit line gating unit, a data reading unit, and an analog voltage generating unit. During data writing, a source is floated, and a well electrode is connected to ground; and a first forward voltage is applied to a bit line where a memory cell to be written data into is located, and a second forward voltage is applied to a word line where the memory cell to be written data into is located. During data reading, a source is grounded, and well electrodes are grounded; and a third forward voltage is applied to a word line.

Nor flash memory circuit and data writing method

Disclosed herein is an apparatus and method for a shuffle manager for a distributed memory object system. In one embodiment, a method includes forming a system cluster comprising a plurality of nodes, wherein each node includes a memory, a processor and a network interface to send and receive messages and data, wherein the network interface operates on remote direct memory access; creating a plurality of sharable memory spaces having partitioned data, wherein each space is a distributed memory object having a compute node, wherein the sharable memory spaces are at least one of persistent memory or DRAM cache; and storing data in an in-memory data structure when there is available memory in a compute node; and if there is an out of memory condition, serializing at least some of the in-memory data and spilling it to a distributed memory object system to persist shuffled data outside the compute node.

Shuffle manager in a distributed memory object architecture

Disclosed herein is a persistent memory (PMEM)-based distributed memory object system, referred to as the PMEM DMO system, that provides affordable means of integrating low-latency PMEM spaces with other devices, including servers that do not directly support PMEM. One embodiment comprises providing a cluster of servers with PMEM storage (PMEM servers) and connecting the PMEM servers to a plurality of applications servers using a low-latency network, such as a remote direct memory access; background processes on each of the application servers are tasked to perform input/output operations for the application servers to locally materialize objects from and synchronize/persist objects to the remote PMEM spaces on the PMEM servers. Data materialized from the PMEM servers is stored to the local cache of the application server for use. Also disclosed are data eviction policies for clearing the local cache of the application servers to make space for new data read.

Cost-effective deployments of a PMEM-based DMO system

Disclosed herein is an apparatus and method for a distributed memory object system. In one embodiment, a method includes forming a system cluster comprising a plurality of nodes, wherein each node includes a memory, a processor and a network interface to send and receive messages and data; creating a plurality of sharable memory spaces having partitioned data, wherein each space is a distributed memory object having a compute node, wherein the sharable memory spaces are at least one of persistent memory or DRAM cache; at a client, establishing an inter process communication between the client and a distributed memory object service; receiving a meta chunk including attributes about a file and a chunk map from a distributed memory object service, wherein the meta chunk includes chunk information including identity and location of a data chunk; and the client mapping the data chunk into virtual memory address space and accessing it directly.

Distributed memory object apparatus and method enabling memory-speed data access for memory and storage semantics

Techniques are disclosed for monitoring the performance of transient virtual volumes created for a virtual machine. Each transient virtual volume is created in response to a first trigger event, used by the virtualization environment solely to perform a single function supporting execution of the virtual machine, and deleted in response to a second trigger event. When creation of a current transient virtual volume is detected, and while the virtualization environment uses the current transient virtual volume to perform a single function supporting execution of the virtual machine, performance data is collected for the current transient virtual volume, and combined with performance data collected for at least one other, previously deleted transient virtual volume that was used solely to perform the same single function supporting execution of the same virtual machine. The combined performance data is represented as performance data for a single monitored virtual volume associated with the virtual machine.

Monitoring performance of transient virtual volumes created for a virtual machine

Techniques for visualizing performance of file-based VVols and block-based VVols for aiding in administration of a data storage system operating in a virtualization environment allow performance of these different types of VVols to be visualized side-by-side using a common set of performance metrics. Thus, in one embodiment, the performances of file-based and block-based VVols are both converted into a mutually-compatible format and rendered for display together on screen.

Techniques for converging metrics for file- and block-based VVols

Techniques for visualizing performance of VVols for aiding in administration of a data storage system operating in a virtualization environment allow performance of these VVols to be visualized in a highly-flexible manner. Thus, in one embodiment, the performances of all VVols within a storage container are aggregated together for easy comparison among the aggregated performances of different storage containers.

Techniques for aggregating metrics for VVols within a storage container

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Shanghai, China

Yue Zhao