United Microelectronics Corp.

Yue-Shiun Lee

Cheng-Hsiung Chen

Gary Y Hong

Yuan-Chang Liu

Tsz-Hui Kuo

Shyh-Jye Lin

Meng-Fan Wang

Heng-Seng Huang

The present invention provides a differential varactor device including a substrate having a first conductive type, a well having a second conductive type, five doped regions having the second conductive type, a first gate, a second gate, a third gate, and a fourth gate. The well is disposed in the substrate, and the doped regions are disposed in the well and arranged along a direction. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the well between any two of the adjacent doped regions, and are arranged sequentially along the direction.

Differential varactor device

A method of characterizing semiconductor device includes providing a silicon-on-insulator (SOI) substrate with at least a body-tied (BT) SOI device and a BT dummy device for measurement, respectively measuring tunneling currents (I) and scattering parameters (S-parameters) of the BT SOI device and the BT dummy device, subtracting Iof BT dummy device from that of the BT SOI device to obtain Iof a floating body (FB) SOI device, filtering characteristics of the BT dummy device out to extract S-parameters of the FB SOI device, and analyzing the S-parameters of the FB SOI device to obtain gate-related capacitances of the FB SOI device.

Method of characterizing a semiconductor device and semiconductor device

A radio frequency test key structure includes a substrate, a bottom metal layer and a top metal layer. A narrow testing region is defined on the substrate. The bottom metal layer is positioned on the substrate and in the narrow testing region, and including an opening to expose parts of a device under test. The top metal layer is a metal pad in a sheet form, positioned in the narrow testing region and on the bottom metal layer. At least two signal pad regions and at least two ground pad regions are defined in the top metal layer. The signal pad regions and the ground pad regions are arranged in one row, and the row is parallel to the narrow testing region. Accordingly, the radio frequency test key structure can be positioned in a scribe line, and get an accurate testing result.

Radio frequency test key structure

A method of manufacturing a resistor is provided. At first, a semiconductor layer including at least a high resistance region and a low resistance region is formed on a substrate. Following that, a first ion implantation process is performed to the entire surface of the semiconductor layer, and a second ion implantation process is performed to the portions of the semiconductor layer within a predetermined region, so that the semiconductor layer has a higher doping concentration within the predetermined region than in the other regions. Therein, the predetermined region overlaps the low resistance region, the junction between the low resistance region and the high resistance region, and the portions of the high resistance region adjacent to the junction between the low resistance region and the high resistance region.

Method for manufacturing a resistor

A resistor structure includes a substrate, a semiconductor layer positioned on the substrate, a salicide block positioned on portions of the surface of the semiconductor layer, and at least a salicide layer positioned on the portions of the surface of the semiconductor layer adjacent to the salicide block. The semiconductor layer has a predetermined region overlapping the salicide layer, the junction between the salicide layer and the salicide block, and the portions of the salicide block adjacent to the junction between the salicide layer and the salicide block. The semiconductor layer has a higher doping concentration within the predetermined region than in the other regions.

Resistor structure and method for manufacturing the same

Equivalent circuits and a simulation method for simulating an RF switch are disclosed. The equivalent circuits are a first equivalent circuit and a second equivalent circuit, and are formed by resistors, capacitors, and inductors. The method includes using the first equivalent circuit to simulate the switch at a turned-off state and using the second equivalent circuit to simulate the switch at a turned-on state.

Equivalent circuits and simulation method for an RF switch

The present invention provides a C-V method for measuring an effective channel length in a device, which can simultaneously measure a gate-to-drain overlap length and a gate etch bias length in the device. In the present method, the measured length of the gate by using the present method has a deviation below 5% compared with the real gate length form SEM. Furthermore, the calculating method of the present invention only uses simple simultaneous equations, which can be measured by a man or a mechanism. As the layout rule shrunk, the present method provides a simple way to measure those parameters, which have become more and more important in the device.

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Taipei, Taiwan

Yue-Shiun Lee