Shanghai Tianma Am-oled Co., Ltd.

Wuhan Tianma Micro-electronics Co., Ltd

Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch

Tianma Micro-electronics Co., Ltd.

Yangtze Memory Technologies Co., Ltd.

Novartis Ag

Ovg Vacuum Technology (shanghai) Co., Ltd.

Shanghai Tianma Micro-electronics Co., Ltd.

Astex Therapeutics Limited

Other

Emc IP Holding Company LLC

Hach Company

Smartsens Technology (hk) Co, Limited

03;tianma Micro-electronics Co., Ltd.

Tianma Micro-electornics Co., Ltd.

Yue Ping Li

Dongxu Xiang

Xingyao Zhou

Renyuan Zhu

Yana Gao

Mengmeng Zhang

Gang Liu

Zhonglan Cai

Zeyuan Chen

Dong Qian

Gaojun Huang

Tong Wu

Shuai Yang

Juan Zhu

Yilin Xu

Chun Yuan Hou

Yuantao Wu

Yuan Wx Li

Xinzhao Liu

Kaihong Huang

Zhi Liu

Yi Rong

Miaole Shen

Feng He

Lei Liu

Yuan Mi

Tong Zhang

Zhengtian Yu

Guoliang Xun

Miao Dai

Ji Yue Zhang

Jing Huang

Zhe Zhao

Yao-Chang Xu

Xingnian Fu

Miles Stuart Congreve

Peng Zhang

Lijing Han

Steven Howard

Lei Jiang

Bharat Lagu

Gilbert Besong

Troy Douglas Smith

Chuanli Leng

Christopher Thomas Brain

Fang Liang

Moo Je Sung

Jian Kuang

Guo He

Claudio Dagostin

Wojciech Wrona

Yipin Lu

Ying Hou

Paul Mortenson

Wei Jun Wan

Xueqi Tian

Clinton Alan Brooks

Xiaoxia Yan

Xing Yao Zhou

Haojie Xu

Tao Peng

Huijun Jin

Yaowu Mo

Min Chen

Huiping Chai

Yu Xin

Gujun Li

Liyuan Luo

Jun Zhu

Qingxia Wang

Xiangzi Kong

Steven John Woodhead

Xiaoye Li

Guanjing Ren

Wei Wang

Chang-ho Tseng

Zhuan Gao

Di Zhu

Lilian Kuang

Steven Woodhead

Yujiao Liang

Mark Mao

Zhiliang Wang

Yi Du

Jinjian Hou

Bozhang Sun

Minfu Zhang

Wenhui Zou

Yueting Fang

Chunyang Li

Fan Zhao

Jieliang Li

Ranran Zeng

Edward Xu

Neil Yongjing Wang

Sam Lei Sun

Fei Wu

Gao Yana

Display panel and display device are provided. The display panel includes a display area and a non-display area surrounding the display area. The display area includes a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction, the first direction intersects the second direction. The non-display area includes a bonding area. The bonding area includes a plurality of pads arranged in a third direction. A direction perpendicular to the third direction is a fourth direction. An angle formed by the second direction and the fourth direction is θ, and 0°<θ<90°.

Display panel and display device

A driving circuit and a display panel are provided. The driving circuit includes a pixel circuit and a demultiplexing circuit. The pixel circuit includes a driving transistor, a light-emitting device, and a data writing module. The driving transistor is connected between a first power signal terminal and the light-emitting device in series, to generate a driving current. The data writing module is connected between the driving transistor and the demultiplexing circuit in series, to provide a data signal to the driving transistor. An output terminal of the demultiplexing circuit is connected to an input terminal of the data writing module through a data line. The demultiplexing circuit is configured to write the data signal to the data line when the driving transistor is performing threshold compensation.

Driving circuit, driving method, and display panel

Provided are a display panel and a driving method for a display panel. The display panel includes multiple levels of shift registers which are cascaded, a clock signal line and a trigger signal line. The display panel comprises a current display mode which comprises a current FPS, a current trigger signal and a current clock signal, where the current FPS is the same as a refresh frequency of the current trigger signal. The display panel further comprises a reference display mode which comprises a reference FPS, a reference trigger signal and a reference clock signal. An effective action duration of the current trigger signal comprises a first stage, and in the first stage, a pulse width of the current clock signal is the same as a pulse width of the reference clock signal. The current FPS is less than a reference FPS in the reference display mode.

Display panel and driving method of a display panel

The present application provide a pixel circuit and a driving method thereof, and a display panel. The pixel circuit includes: a driving module, a control end of the driving module being electrically connected to a first node; a threshold compensation module, electrically connected to a first scan signal line, the first node, and a first end of the driving module; a first switch module, electrically connected to a first light emitting control signal line and the first end of the driving module; a second switch module, electrically connected to a second light emitting control signal line, a second end of the first switch module, and a first electrode of a light emitting element; and a voltage regulator module, electrically connected to a constant voltage signal line and a target node.

Pixel circuit and driving method thereof, and display panel

A driving method of a display panel and a display panel are provided. Time for displaying one frame includes N times of first node potential adjustment stages, a data writing stage, and at least one first bias stress stage; the data writing stage is after the first node potential adjustment stage and before the first bias stress stage; the N times first node potential adjustment stage include N reset stages and N first adjustment voltage writing stages; and an i-th first voltage writing stage is after an i-th reset stage. In the reset stage, the first reset module is turned on to write a reset signal to the first node; in the first adjustment voltage writing phase, the first reset module is turned off, and the compensation module is turned on to write a first adjustment voltage into the first node to adjust the bias state of the driving transistor.

Driving method of display panel, and display device

A three-dimensional (3D) memory device includes a 3D NAND memory array, an on-die static random-access memory (SRAM), and peripheral circuits formed on the same chip with the on-die SRAM. The peripheral circuits include a page buffer coupled to the on-die SRAM and a controller coupled to the on-die SRAM and the page buffer. The controller may be configured to load program data into the page buffer and cache the program data into the on-die SRAM as a backup copy of the program data. In response to a status of programming the program data from the page buffer into the 3D NAND memory array being failed, the controller may be further configured to transmit the backup copy of the program data in the on-die SRAM to the page buffer, and program the backup copy of the program data in the page buffer into the 3D NAND memory array.

Cache program operation of three-dimensional memory device with static random-access memory

A shift register includes a plurality of cascaded shift register circuits. The first control module of a shift register circuit controls the potential of a first node according to a first clock signal, a second clock signal, and the potential of the first node. A second control module controls the potential of a second node according to the first level signal of a third clock signal and the potential of the first node. An output module controls, according to the potential of the first node, the time of outputting the first level signal and controls, according to the potential of the second node, the time of outputting a second level signal. In a data writing phase, the third clock signal includes a plurality of effective pulses. In at least in a first retention frame, the third clock signal is an ineffective fixed level.

Shift register, display panel, and display apparatus

A display panel includes: a plurality of light-emitting pixels arranged in an array, a first shift register unit and a second shift register unit, wherein the first shift register unit is connected to data writing transistors in an irow and an (i+1)row and configured to provide a first controlling signal for the two adjacent rows of pixel circuits, and the data writing transistor is turned on in response to the first controlling signal; the second shift register unit is connected to threshold compensating transistors in the irow and an (i−1)row, and configured to provide a second controlling signal for the two adjacent rows of pixel circuits, and the threshold compensating transistor is turned on in response to the second controlling signal; and wherein a first turn-on period of the data writing transistor is partially overlapped with a second turn-on period of the threshold compensating transistor.

A display panel, a method for driving a display panel, and a display device are provided. A first scanning driving unit is electrically connected to first scanning control terminals of first and second pixel driving circuits. A working cycle of the pixel driving circuit includes a data writing phase. The data writing phase of the first pixel driving circuit is prior to the data writing phase of the second pixel driving circuit in a display duration of one frame of an image. When the first pixel driving circuit and the second pixel driving circuit receive a same data voltage, a potential Vof the first node in the first pixel driving circuit after the data writing phase of the first pixel driving circuit is greater than a potential Vof the first node in the second pixel driving circuit after the data writing phase of the second pixel driving circuit.

Display panel, method for driving display panel, and display device

Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.

Data buffering operation of three-dimensional memory device with static random-access memory

Provided are a display panel and a display device. The display panel includes a base substrate as well as, at a side of the base substrate, a plurality of sub-pixels arranged in an array, a power bus, a plurality of first power lines extending along a column direction and a plurality of second power lines extending along a row direction, where each of the plurality of first power lines is electrically connected to the plurality of the sub-pixels arranged along the column direction, and the plurality of first power lines and the plurality of second power lines are electrically connected in overlapping regions of vertical projection on the base substrate. The display panel further includes a plurality of connection units.

A display panel and a display device are provided. In an embodiment, the display panel has a display region and a non-display region and includes shift registers cascaded and arranged along a first direction. In an embodiment, the shift registers are located in the non-display region. In an embodiment, one of the shift registers includes a switch module and an output module. In an embodiment, the output module is coupled to an output terminal of the shift register and includes two output transistors, and the output transistors are located at a side of the switch module away from the display region. In this way, the probability of occurrence of abnormal phenomena, such as splash screen display, is reduced.

Provided are a display panel, a driving method, and a display device. The display panel includes: a gate driving circuit, a pixel driving circuit, and a light-emitting component. The pixel driving circuit includes a driving transistor, a data writing module, a threshold compensation module, and a light-emitting control module. A transistor in the threshold compensation module is a P-type transistor and a transistor in the light-emitting control module is an N-type transistor, or the transistor in the threshold compensation module is an N-type transistor and the transistor in the light-emitting control module is P-type transistor. A control terminal of the threshold compensation module and a control terminal of the light-emitting control module are electrically connected to a same gate driving circuit.

Display panel with narrow frame width, driving method of display panel with narrow frame width and display device with narrow frame width

A display panel, a method for driving the same, and a display apparatus are provided. A pixel driving circuit includes a driving transistor, a data writing circuit, and an adjusting circuit. The driving transistor has a gate electrically connected to a first node, and first and second electrodes respectively electrically connected to a second node and a third node. An operating period of the pixel driving circuit comprises a data writing period including first and second adjusting stages and a data writing period between the first and second adjusting stages. A data writing circuit is configured to provide a data signal to the second node during the data writing period. An adjusting circuit is configured to provide a first adjusting signal to the second node or the third node during the first adjusting stage, and to provide a second adjusting signal to the second node during the second adjusting stage.

Display panel, method for driving the same, and display apparatus

A display panel, a driving method of a display panel, and a display device are provided. The display panel includes pixel circuits and a gate driving circuit including cascaded first shift register units. A trigger signal input terminal of the first stage first shift register unit is connected to a trigger signal terminal through a first switch element. A signal output terminal of the i-th stage first shift register unit is connected to a trigger signal input terminal of the (i+1)-th stage first shift register unit through a second switch element. A trigger signal input terminal of the N-th stage first shift register unit is connected to the trigger signal terminal through a third switch element. A signal output terminal of the j-th stage first shift register unit is connected to a trigger signal input terminal of the (j&#x2212;1)-th stage first shift register unit through a fourth switch element.

Display panel, driving method, and display device with real time switch of forward and reverse scanning

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Wuhan, China

Yue Ping Li