National Central University

Delta Electronics, Inc.

Yue-Ming Hsin

Jinn-Kong Sheu

Kuang-Po Hsueh

Fang-Ping Chou

Ching-Wen Wang

Chun-Chieh Yang

Guan-Yu Chen

Yi-Nan Zhong

Yu-Chen Lai

Zi-Ying Li

A device includes a first transistor and a second transistor. The first transistor includes a first gate terminal coupled to the first source terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal coupled to the first drain terminal, a second source terminal, and a second drain terminal.

Device and semiconductor structure for improving the disadvantages of p-GaN gate high electron mobility transistor

A silicon photodiode with symmetry layout and deep well bias in CMOS technology is provided. The silicon photodiode includes a substrate, a deep well, and a PN diode structure. The deep well is disposed on the substrate, where an extra bias is applied to the deep well. The region surrounded by the deep well forms the main body of the silicon photodiode. The PN diode structure is located in the region surrounded by the deep well, where the silicon photodiode has a symmetry layout. The deep well is adopted when fabricating the silicon photodiode, and the extra bias is applied to the deep well to eliminate the interference and effect of the substrate absorbing light, and further greatly improve speed and bandwidth. Furthermore, the silicon photodiode has a symmetry layout, so that uniform electric field distribution is achieved, and the interference of the substrate noise is also reduced.

Si photodiode with symmetry layout and deep well bias in CMOS technology

A lateral avalanche photodiode structure including a substrate, a PN diode and a metal layer is provided. The substrate has at least one first electrode area, at least one light receiving area, and at least one second electrode area which are arranged horizontally. The first electrode area is also an avalanche area, and the light receiving area is between the first electrode area and the second electrode area. The PN diode is disposed in the substrate in the first electrode area. The metal layer is disposed on the substrate and covers the first electrode area and the second electrode area, but does not cover the light receiving area.

Lateral avalanche photodiode structure

A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

Method of forming a planar combined structure of a bipolar junction transistor and n-type and p-type metal semiconductor field-effect transistors and method for forming the same

A gallium nitride heterojunction bipolar transistor with a p-type strained InGaN base layer is provided. The gallium nitride heterojunction bipolar transistor includes a substrate, a highly doped collector contact layer located over the substrate, a low doped collector layer located over the collector contact layer, a p-type base layer located over the collector layer, a highly doped strained InGaN base layer located over the p-type base layer, a emitter layer located over the p-type strained InGaN base layer, a highly doped emitter contact layer located over the emitter layer, and an emitter metal electrode, a base metal electrode, and a collector metal electrode respectively located on the emitter contact layer, the p-type strained InGaN base layer, and the collector contact layer.

Growing community of inventors

Tainan, Taiwan

Yue-Ming Hsin