International Business Machines Corporation

Globalfoundries Inc.

Qualcomm Incorporated

Leland Stanford Junior University

Yue Liang

Xiaojun Yu

Brian Joseph Greene

William K Henson

Dureseti Chidambarrao

Michael Patrick Chudzik

Shreesh Narasimha

Yanfeng Wang

Dechao Guo

Ravikumar Ramachandran

Unoh Kwon

Sunfei Fang

Jun Yuan

Rashmi Jha

Edward J Nowak

Shu-Jen Han

Kern Rim

Qingqing Liang

Richard Stephan Wise

Eduard Albert Cartier

Xinlin Wang

Edward P Maciejewski

Ricardo Alves Donaton

Myung-Hee Na

Wiliam K Henson

Takashi Ando

Chun-chen Yeh

Vijay Narayanan

Keith Kwong Hon Wong

Haizhou Yin

Martin Michael Frank

Hrishikesh Vijaykumar Panchawagh

Siddarth A Krishnan

Kailash Gopalakrishnan

Jessica Liu Strohmann

Yipeng Lu

Ming Cai

James D Plummer

Maryjane Brodsky

Liyang Song

Changting Xu

Peter B Griffin

An example method of operation may include detecting a user touch in a first area based upon sensor data from one or more sensors of a first type, waking up one or more sensors of a second type configured to measure across some or all of the first area in response to the detecting, obtaining additional sensor data from the one or more sensors of the second type, and determining a location associated with the user touch based in part upon the sensor data from the one or more sensors of the second type.

Temperature and ultrasonic sensor fusion for biometric sensing

A method including forming a structure including a plurality of semiconductor devices surrounded by a dielectric layer such that a top surface of the dielectric layer is substantially flush with a top surface of the plurality of semiconductor devices, depositing a thermal optimization layer above the structure, patterning the thermal optimization layer such that a portion of the thermal optimization layer is removed from a above first region of the structure and another portion of the thermal optimization layer remains above a second region of the structure, the first region having a different thermal conductivity than the second region, and heating the structure, the patterned thermal optimization layer causing substantially uniform thermal absorption of the structure.

Semiconductor process temperature optimization

In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

Tucked active region without dummy poly for performance boost and variation reduction

A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1&#xd7;10atoms/cmto 1&#xd7;10atoms/cmis present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.

Work function adjustment by carbon implant in semiconductor devices including gate structure

A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor

A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

Threshold voltage adjustment for thin body MOSFETs

A method of forming a semiconductor device comprising a dummy gate interconnect includes forming a dummy gate on a substrate, the dummy gate comprising a dummy gate metal layer located on the substrate, and a dummy gate polysilicon layer located on the dummy gate metal layer; forming an active gate on the substrate, the active gate comprising an active gate metal layer located on the substrate, and an active gate polysilicon layer located on the active gate metal layer; and etching the dummy gate polysilicon layer to remove at least a portion of the dummy gate polysilicon layer to form the dummy gate interconnect, wherein the active gate polysilicon layer is not etched during the etching of the dummy gate polysilicon layer.

Dummy gate interconnect for semiconductor device

A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source/drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.

Method and structure for pFET junction profile with SiGe channel

A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.

MOS having a sic/sige alloy stack

Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.

Post-gate shallow trench isolation structure formation

Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state.

Programmable FETs using Vt-shift effect and methods of manufacture

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Beacon, NY, United States of America

Yue Liang