Vanguard International Semiconductor Corporation

Realtek Semiconductor Inc.

Yue-Feng Chen

Erik S Jeng

Hung-Yi Luo

Liang-Gi Yao

Chen-Tung Lin

Chung-Ju Lee

Ing-Ruey Liaw

Bi-Ling Chen

Wei-Ray Lin

Yeur-Luen Tu

Ming-Horn Tsai

Wen-Tsing Tzeng

Jui-Hsiang Yang

Dong Fang

Kau-Jan Wang

Guo-Dong Gao

Guei-Chi Guo

A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a privilege area and a normal area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a privilege mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Direct memory access (DMA) controller, electronic device using the DMA controller and method of operating the DMA controller

A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a secure area and a non-secure area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a secure mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

A method for real-time firmware configuration and a debugging apparatus are provided. When a demand for updating or debugging a target processor raises, in the method, a computer system generates a firmware debugging request that is attached with a firmware data with a specific debugging function. The computer system then loads the firmware data to a programmable logic unit of the debugging apparatus. After the real-time firmware configuration is completed, the computer system issues a debugging command to the programmable logic unit. The programmable logic unit obtains at least one debugging action after resolving the debugging command. The at least one debugging action is performed in the target processor when the target processor receives the at least one debugging action. A debugging result is returned after the at least one debugging action is completed.

Method for real-time firmware configuration and debugging apparatus

A fabrication method for flash memory. The method comprises providing a substrate, and a first insulation layer, a first conductive layer, a second insulation layer thereon. The second insulation layer is patterned to form a first opening and reveal a part of the first conductive layer, and a third insulation layer is formed on the first opening sidewall to form a second opening. The first conductive layer and the first insulation layer beneath the second opening are etched to expose the substrate surface, and a spacer is formed on the second opening sidewall. A source region is formed in the exposed substrate and a source line with a concave surface is formed in the second opening. A mask layer is formed on the source line concave surface.

Fabrication method for flash memory source line and flash memory

A method is described for progressively forming a fuse access opening for laser trimming in an integrated circuit with improved control of dielectric thickness over the fuse. A dielectric layer is formed over the fuse and a polysilicon layer is then patterned over the fuse to form a first etch stop. An ILD layer is added and a second etch stop is formed in a first metal layer on the ILD layer over the first etch stop. The second etch stop serves to protect the ILD layer over the fuse from being etched by an ARC over etch during the via etching in a first IMD layer. A first portion of the laser access window is formed during the via etching of the first IMD layer. The second etch stop is then removed by the second metal patterning etch, exposing the ILD layer over the first etch stop at it's original thickness. A passivation layer is deposited and patterned to form access openings to bonding pads as well as to further open the laser access window to the first etch stop. The first etch stop prevents penetration of the subjacent insulative layer over the fuse, thereby maintaining a controlled uniform thickness of that layer. When the bonding pads are opened, including the removal of an ARC on their surface, the etchant conditions are changed to remove the etch stop and subsequently a portion of the subjacent insulative layer over the fuse leaving a precise and uniform thickness of dielectric material over the fuse. The process fits conveniently within the framework of an existing process and does not introduce any additional steps.

Process for controlling oxide thickness over a fusible link using transient etch stops

The present invention includes forming polysilicon plugs between the gate structures and word lines in a BPSG layer formed on the gate structures and the word lines. A polysilicon layer, a tungsten silicide layer and a silicon oxide layer are sequentially formed on the BPSG layer. Then, the multi-layers are etched to the surface of the BPSG layer. Next, the BPSG layer is slightly etched to expose the polysilicon plug. Oxide spacers are formed on the sidewalls of the layers. A silicon nitride layer is formed over the bit lines, oxide spacers and on the polysilicon plugs. An oxide layer is formed on the silicon nitride layer. Subsequently, the oxide layer is patterned to form node contact holes. An etching is used to etch the silicon nitride layer. A first conductive layer is formed along the surface of the oxide layer, the contact holes. The top portion of the first conductive layer is removed. The oxide layer is removed to expose the silicon nitride layer. A dielectric film is deposited along the surface of the first conductive layer. Finally, a second conductive layer is formed over the dielectric film.

Method of forming a cob dram by using self-aligned node and bit line

A method of planarizing a structure having an interpoly layer is disclosed. The method includes forming an undoped silica glass layer on at least a polysilicon region formed on a semiconductor substrate. Next, a spin-on-glass layer is formed over the undoped silica glass layer. Finally, the spin-on-glass layer is etched back, thereby planarizing the structure having the interpoly layer.

Method of planarizing a structure having an interpoly layer

A process for creating a crown shaped storage node structure, for a DRAM capacitor structure, featuring the use of a silicon oxynitride layer, underlying the crown shaped storage node structure, has been developed. A silicon oxynitride layer is placed overlying the interlevel dielectric layers that used to protect underlying DRAM elements, and placed underlying a capacitor opening in an overlying insulator layer. A selective RIE procedure is used to create the capacitor opening, in an insulator layer, with the RIE procedure terminating at the exposure of the underlying silicon oxynitride layer. After creation of the crown shaped storage node structure, in the capacitor opening, overlying the silicon oxynitride layer at the bottom of the capacitor opening, the insulator layer used for formation of the capacitor opening, is selectively removed from the regions of silicon oxynitride layer, not covered by the overlying crown shaped storage node structure, using wet etch procedures.

Etch stop layer used for the fabrication of an overlying crown shaped

A method of fabricating contact holes in high density integrated circuits uses landing plugs to reduce the aspect ratio of the the node contact holes in order to improve the processing window of deep contact holes. Along with nitride spacers on the sidewalls of a transistor gate structure, polysilicon hard masks and polysilicon spacers are used as etching masks in a self-aligned contact process. In addition, the landing plugs incorporate the polysilicon spacers as part of landing plug to increase the contact area. As a result, wide contact processing windows can be achieved in high density integrated circuits.

Method of fabricating contact holes in high density integrated circuits

A method for forming a self-aligned contact, (SAC), opening, for a semiconductor device, has been developed. The process features the formation of partial silicon nitride spacers, on the sides of polycide gate structures, via a partial anisotropic RIE procedure, applied to a silicon nitride layer, also resulting in a thin layer of silicon nitride remaining on regions between polycide gate structures. After deposition of an overlying insulator layer, a two step, anisotropic RIE procedure is used to create the SAC opening in the insulator layer, and in the underlying, thin silicon nitride layer. The first step, of the two step, SAC opening procedure, selectively removes first insulator layer, while the second step, of the two step, SAC opening procedure, selectively removes the thin silicon nitride layer.

Method of fabricating sidewall spacers for a self-aligned contact hole

A method for forming a contact hole of a capacitor of a DRAM cell is disclosed. The method includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the semiconductor substrate and the first dielectric layer. Next, the second dielectric layer is anisotropically etched back to form a first spacer on sidewalls of the first dielectric layer and the first conductive layer. A first silicon oxide layer is formed over the semiconductor substrate, the first dielectric layer, the first spacer, followed by patterning to etch the first silicon oxide layer, wherein the first spacer and the first dielectric layer are used for facilitating self-aligned etching. Thereafter, a second conductive layer is formed over the semiconductor substrate, wherein surface of the first silicon oxide layer is exposed, and a second silicon oxide layer is formed over the second conductive layer and the first silicon oxide layer. Finally, patterning to etch a portion of the second silicon oxide layer to expose a portion of the second conductive layer, therefore a contact hole of the capacitor is formed.

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Hsinchu, Taiwan

Yue-Feng Chen