Macronix International Co., Ltd.

Megachips Corporation

Yuchih Yeh

Naiping Kuo

Nai-Ping Kuo

Yi-Chun Liu

Yuko Tamagawa

Shihchou Juan

Jianshing Liu

Naping Kuo

Chin Chu Chung

Methods, devices, systems, and apparatus including computer-readable mediums for managing memory reliability in memory systems are provided. In one aspect, a memory system includes a memory device having a plurality of blocks and a memory controller coupled to the memory device. The memory controller is configured to send a read command to the memory device, and the read command includes address information of at least one block in the memory device. The memory device is configured to: determine whether the read command comprises an indication for enabling adjusted read level determination, in response to determining that the read command comprises the indication for enabling the ARL determination, determine at least one adjusted read voltage for the at least one block, and execute a read operation based on the at least one adjusted read voltage according to the read command.

Managing memory reliability in memory systems

A method for sensing temperature in memory die, memory die and memory with temperature sensing function are provides. The memory die includes at least one temperature monitoring for outputting a temperature status in the memory die; a temperature sensor, arranged in the memory die for sensing an operation temperature in the memory die; and a control logic unit, coupled to the temperature sensor for receiving the operation temperature and coupled to the temperature monitoring pin. The control logic unit compares the operation temperature and a threshold value received from outside of the memory die to generate a comparison result, and outputs the temperature status through the temperature monitoring according to the comparison result.

Method for sensing temperature in memory die, memory die and memory with temperature sensing function

Methods, systems and apparatus including computer-readable mediums for rearranging data for refresh operations in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: determining that a particular logical page in a logical block fails based on error bits in a particular physical page that is in a first physical block mapped with the logical block and corresponds to the particular logical page, logical pages in the logical block being mapped to physical pages in the first physical block with an initial mapping order, and executing a refresh operation on the first physical block with a rearranged mapping order for the logical block, the rearranged mapping order being different from the initial mapping order. For the refresh operation, the logical pages in the logical block are mapped to physical pages in a second physical block with the rearranged mapping order.

Rearranging data in memory systems

Systems, methods, and apparatus including computer-readable mediums for detecting data integrity, e.g., read disturbance and/or data retention, of memory systems such as NAND flash memory devices are provided. For detection of read disturbance, an indicator string in a block of a memory can be filled with a predetermined state and read with a special read condition to check read disturbance of the block in one read operation. For detection of data retention, a page of a dedicated block in a memory can be chosen as an indicator page. The indicator page can be filled with a predetermined pattern and read with a proper voltage to quantify a retention shift and further to evaluate other data blocks in the memory with the qualified retention shift. The techniques enable a quick method to examine memory and help to refresh memory before data corruption.

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Hsin-Chu, Taiwan

Yuchih Yeh