Samsung Electronics Co., Ltd.

Yubo Qian

Sungho Park

Byungju Kang

Seonah Nam

Hyelim Kim

Byungsung Kim

Chul Hong Park

Byung Sung Kim

Young Gook Park

Hyeon Uk Kim

Chul-hong Park

Byung-Sung Kim

Haewang Lee

A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

Semiconductor devices with circuit active elements and dummy active elements

Semiconductor devices with circuit and external dummy areas

A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.

Semiconductor devices

Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode.

Semiconductor device having shared power line connections and method of manufacturing the same

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Yongin-si, South Korea

Yubo Qian