Alibaba Group Holding Limited

C-sky Microsystems Co., Ltd.

Alipay (hangzhou) Information Technology Co., Ltd.

Yubo Guo

Zhijian Chen

Jiahui Luo

Wenmeng Zhang

Ying Yan

Changzheng Wei

Lei Zhang

Chen Chen

Taotao Zhu

Guozhen Pan

Xuepeng Guo

Dingyan Wei

Ren Guo

Manzhou Wang

Haiyuan Gao

Qibin Ren

Zucheng Huang

Kuan Zhao

Zhesheng Luo

A processor achieving a zero-overhead loop, includes instruction stream control circuitry and loop control circuitry. The loop control circuitry includes loop address detecting circuitry and loop end determining circuitry. By combining instructions and hardware, the loop control circuitry eliminates additional control instructions required b each loop iteration and can achieve loop acceleration with zero overhead, thereby improving the loop execution efficiency.

Processor for executing a loop acceleration instruction to start and end a loop

A first logic circuit included in a processor receives a first digital signal, where the first logic circuit includes a special purpose register, a comparator, and an adder, where the special purpose register stores a first resource balance for executing a smart contract, where the first digital signal includes a resource deduction quota corresponding to a code set in the smart contract. The first logic circuit reads the first resource balance from the special purpose register. The first logic circuit compares, using the comparator, the first resource balance with the resource deduction quota. In response to the first resource balance being greater than or equal to the resource deduction quota, the first logic circuit subtracts, using the adder, the resource deduction quota from the first resource balance to obtain a second resource balance. The first logic circuit stores the second resource balance in the special purpose register.

Methods and processors for performing resource deduction for execution of smart contract

The present invention discloses an instruction processing apparatus, comprising a first register adapted to store first source data, a second register adapted to store second source data, a third register adapted to store accumulated data, a decoder adapted to receive and decode a multiply-accumulate instruction, and an execution unit. The multiply-accumulate instruction indicates that the first register serves as a first operand, the second register serves as a second operand, the third register serves as a third operand, and a shift flag. The execution unit is coupled to the first register, the second register, the third register, and the decoder, and configured to execute the decoded multiply-accumulate instruction so as to acquire the first source data from the first register and acquire the second source data from the second register, perform a multiplication operation on the first source data and the second source data so as to obtain a multiplication result, shift the multiplication result according to the shift flag, and add the shifted multiplication result and the accumulated data in the third register so as to obtain a multiply-accumulate result. The present invention further discloses a corresponding instruction processing method, a computing system, and a system on chip.

Multiply-accumulate instruction processing method and apparatus

The present disclosure provides a multi-core processor. The multi-core processor comprises a plurality of cores and a debug circuit, the debug circuit comprising debug circuits in the same number as that of the cores, transmission controllers in the same number as that of the cores, and a master control circuit, each of the debug circuits being connected to one core and one transmission controller, respectively, and all transmission controllers being connected to the master control circuit. Each of the debug circuits is configured to generate a debug event signal and respond to the generated debug event signal or received debug event signals generated by other debug circuits. Each of the transmission controllers is configured to respectively control transmission of the debug event signal between the respectively connected debug circuit and the master control circuit. The master control circuit is configured to forward debug event signals among different transmission controllers. The present disclosure can realize rapid configuration and control of debug event signal transmission, and at the same time lower power consumption of a debug circuit.

Debugging solution for multi-core processors

The present disclosure discloses an instruction processing apparatus, comprising a first vector register adapted to store a first vector to be operated on, a second vector register adapted to store a second vector to be operated on, a decoder adapted to receive and decode a data splicing instruction, and an execution unit. The data splicing instruction indicates the first vector register as a first operand, the second vector register as a second operand, a splicing indicator, and a destination. The execution unit is coupled to the first vector register, the second vector register, and the decoder, and is adapted to execute the decoded data splicing instruction, so as to acquire a first part of the first vector from the first vector register and acquire a second part of the second vector from the second vector register according to the splicing indicator, splice the acquired first part of the first vector and the acquired second part of the second vector to form a third vector, and store the third vector into the destination.

Method and apparatus for processing data splicing instruction

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Hangzhou, China

Yubo Guo