Intel Corporation

Yuanyuan Li

Yong Jiang

Jianghong Du

Kuilin Clark Chen

Thomas A Tetzlaff

Lei Shen

Ravi L Sahita

Selvakumar Panneer

Salmin Sultana

Ruijia Li

Yong Zhang

Danyu Bi

Yanjie Pan

Pramod Pesara

Lingyi Kong

Hai Bai

Guizi Li

Linghyi Kong

Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and broadcast a result of an operation specified in association with the barrier synchronization request.

System and method to accelerate reduce operations in graphics processor

Systems, methods, and computer-readable media are provided for variable precision first in, first out (FIFO) buffers (VPFB) that dynamically changes the amount of data to be stored in the VPFB based on a current amount of data stored in the VPFB and/or based on a current amount of available memory space of the VPFB. The currently unavailable memory space (or the current available memory space) is used to select the size of a next data block to be stored in the VPFB. Other embodiments are disclosed and/or claimed.

Data stored or free space based FIFO buffer

Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.

A system for detecting malware includes a processor to collect processor trace information corresponding to an application being executed by the processor (). The processor can also detect an invalid indirect branch instruction from the processor trace information () and detect at least one malware instruction being executed by the application in response to analyzing modified memory values corresponding to the invalid indirect branch (). Additionally, the processor can block the application from accessing or modifying memory ().

Malware detection in memory

A mechanism is described for facilitating efficient communication and data processing across clusters of computing machines in a heterogenous computing environment. A method includes detecting a request for processing of data using a programming framework and a programming model; facilitating interfacing between the programming framework and the programming model, wherein interfacing includes merging the programming model into the programming framework, wherein interfacing further includes integrating the programming framework with a distribution framework hosting the programming model; and calling on the distribution framework to schedule processing of a plurality of jobs based on the request.

Facilitating efficient communication and data processing across clusters of computing machines in heterogeneous computing environment

Methods and apparatus to improve shared memory efficiency are described. In an embodiment, a first version of a code to access one or more registers as shared local memory is compiled. A second version of the same code is also compiled to access a cache as the shared local memory. The first version of the code is executed in response to comparison of a work group size of the code with a threshold value. Other embodiments are also disclosed and claimed.

Method and apparatus to improve shared memory efficiency

A system and method for distributed computing including a compute node having a graphics processing unit (GPU) to execute tasks of a distributed computing job. A distributed-computing programming framework executes the tasks on the compute node. A GPU-daemon process shares GPU resources between the tasks executing on the GPU of the compute node.

Graphics processing unit operation

An apparatus, method and machine-readable storage medium to improve memory access performance between shared local memory and system global memory are described. The method comprises grouping two or more work groups to form a super workgroup, and positioning a portion of a memory space into one or more super shared local memories (Super SLMs), wherein the memory space which is shared within the super workgroup forms at least one Super SLM of the one or more Super SLMs. The apparatus comprises: a plurality of execution units; a cache memory having a portion which operates as a shared local memory (SLM), which is shared with the plurality of execution units, at least one of which operates on a work group of a sub-slice, wherein the SLM is shared within the work group; and at least one Super-SLM for providing shared memory accessible by different work groups in the sub-slice, wherein the at least one of the execution units operates on the different work groups. A last work group may write data back to a system global memory (SGM) from a Super-SLM.

Growing community of inventors

Shanghai, China

Yuanyuan Li