Suzhou Oriental Semiconductor Co., Ltd.

Suzhou Oriental Semiconductur Co., Ltd.

Yuanlin Yuan

Wei Liu

Lei Liu

Yi Gong

Rui Wang

Zhendong Mao

Xin Wang

Minzhi Lin

Pengfei Wang

Zhenyi Xu

A super junction semiconductor power device includes an n-type drain region, an n-type drift region, multiple p-type columns, a gate structure, and multiple JFET regions. The width of each of the multiple p-type columns is equal. The spacing between two adjacent p-type columns is equal. The tops of the multiple p-type columns are provided with multiple p-type body regions respectively, and the p-type body regions are in one-to-one correspondence with the p-type columns. The widths of the multiple p-type body regions are equal. An n-type source region is provided in each p-type body region. The gate structure is configured to control a current channel between the n-type source region and the n-type drift region to turn on and turn off. The multiple JFET regions are located on the n-type drift region and between adjacent p-type body regions. The multiple JFET regions are provided with at least two different widths.

Super junction semiconductor power device

An IGBT device includes an p-type collector region, an n-type semiconductor layer, several p-type body regions located in the n-type semiconductor layer, a gate trench located in the n-type semiconductor layer and between adjacent p-type body regions, a gate trench located in the n-type semiconductor layer and between adjacent p-type body regions, a shielded gate located in a lower part of the gate trench, and a gate located in an upper part of the gate trench. The gate, the shielded gate, and the n-type semiconductor layer are insulated and isolated from each other. Among the several p-type body regions, at least one p-type body region has a first doping concentration and is defined as a first p-type body region, and at least one p-type body region has a second doping concentration and is defined as a second p-type body region.

Insulated gate bipolar transistor device

An IGBT device includes a p-type collector region, an n-type semiconductor layer located above the p-type collector region, a plurality of gate trenches, shielded gates, gates, and a p-type body region located in the n-type semiconductor layer and between adjacent gate trenches. The gate trenches are located in the n-type semiconductor layer. A shielded gate is located in a lower part of a gate trench. A gate is located in an upper part of the gate trench. The gate, the shielded gate, and the n-type semiconductor layer are insulated and isolated from each other.

Provided is a semiconductor power device. The device includes: at least one p-type body region located on the top of an n-type drift region, a first n-type source region and a second n-type source region located within the p-type body region, a first gate structure configured to control a first current channel between the first n-type source region and the n-type drift region to be turned on or off; and a second gate structure configured to control a second current channel between the second n-type source region and the n-type drift region to be turned on or off. The second gate structure is recessed in the n-type drift region.

Semiconductor power device

Provided is a semiconductor super junction power device which includes a super junction MOSFET cell array composed of multiple super junction MOSFET cells. A gate structure of the super junction MOSFET cell includes a gate dielectric layer, a gate and an n-type floating gate. The gate and the n-type floating gate are located above the gate dielectric layer; the gate is located on a side close to the n-type source region, and the n-type floating gate is located on a side close to the n-type drift region; the gate acts on the n-type floating gate through capacitive coupling. The n-type floating gate of at least one MOSFET cell is isolated from the p-type body region through the gate dielectric layer, and the n-type floating gate of at least one MOSFET cell contacts the p-type body region through an opening in the gate dielectric layer to form a p-n junction diode.

Semiconductor super-junction power device

Provided is an insulated gate bipolar transistor (IGBT) device. The IGBT device includes p-type body regions located on a top of an n-type drift region, a first n-type emitter region located within the p-type body region; a first gate structure located over the p-type body region, where the first gate structure includes a first gate dielectric layer, a first gate and an n-type floating gate which are located above the first gate dielectric layer, where the n-type floating gate is located on a side close to the n-type drift region in a lateral direction; an insulating dielectric layer located between the n-type floating gate and the first gate; and one opening in the first gate dielectric layer. The n-type floating gate is in contact with the p-type body region to form a p-n junction diode through the one opening.

IGBT device

A manufacturing method of a semiconductor super-junction device includes the following steps: An n-type substrate is etched in a self-aligning manner using a first insulating layer and a second insulating layer as a mask to form a second groove in the n-type substrate. A gate structure is formed in the second groove.

Manufacturing method of semiconductor super-junction device

Provided is a semiconductor super junction power device. The semiconductor super junction power device includes an MOSFET cell array composed of multiple super junction MOSFET cells. Each of multiple MOSFET cells includes a p-type body region located at the top of an n-type drift region, a p-type columnar doping region located below the p-type body region, an n-type source region located in the p-type body region, a gate dielectric layer located above the p-type body region, a gate electrode located above the p-type body region, an n-type floating gate located above the p-type body region and an opening located in the gate dielectric layer, where in a lateral direction, the gate electrode is located on one side close to the n-type source region; an opening located in the gate dielectric layer, where the n-type floating gate contacts the p-type body region through the opening to form a p-n junction diode.

Provided is an insulated gate bipolar transistor power device. The IGBT power device includes a gate dielectric layer located above the two p-type body regions and the n-type drift region between the two p-type body regions, an n-type floating gate located above the gate dielectric layer; a gate located above the gate dielectric layer and the n-type floating gate; an insulating dielectric layer between the gate and the n-type floating gate; a first opening located in the gate dielectric layer, where the n-type floating gate is in contact with one of the two p-type body regions through the first opening to form a p-n junction diode; and a second opening located in the gate dielectric layer, where the n-type floating gate is in contact with the other of the two p-type body regions through the second opening to form the p-n junction diode.

IGBT power device

Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

Method for manufacturing a semiconductor super-junction device

Provided is an IGBT power device. The device includes: a p-type collector region; an n-type drift region located above the p-type collector region; multiple first grooves, where a second groove is provided below each of the multiple first grooves; a gate structure located in the first groove and the second groove; a p-type body region located between two adjacent first grooves; an n-type emitter region located in the p-type body region; and an n-type hole charge blocking region located between two adjacent second grooves.

IGBT power device and fabrication method therefor

Disclosed is a power MOSFET device, the power MOSFET device includes a source, a drain, a first gate, a second gate, a body diode, and a body region contact diode. The source, the drain, and the first gate constitute a first MOSFET structure. The source, the drain, and the second gate constitute a second MOSFET structure. A cathode of the body diode is connected to the drain, and an anode of the body region contact diode is connected to an anode of the body diode, a cathode of the body region contact diode is connected to the source. The first gate is configured to control turning on and off of the first MOSFET structure by means of a gate voltage. The second gate is connected to the source and configured to control turning on and off of the second MOSFET structure by means of a source voltage.

Power MOSFET device

Provided is a trench-type power transistor. The trench-type power transistor includes a source, a drain, a first gate, a second gate, a body diode and a body region contact diode. The body diode and the body region contact diode are connected in series. The first gate controls turn-on and turn-off of a first current channel through a gate voltage, the second gate is connected to the source and controls turn-on and turn-off of a second current channel through a source voltage.

Trench power transistor

Disclosed is a semiconductor power device, including a semiconductor substrate; a MOSFET region formed on the semiconductor substrate, where the MOSFET region includes at least one MOSFET unit; and at least one collector region located in the semiconductor substrate, where the collector region and the MOSFET unit form an insulated gate bipolar transistor.

Disclosed is an insulated gate bipolar transistor (IGBT) power device, including a bipolar transistor, a first MOS transistor, a second MOS transistor, a body diode and a body region contact diode. An anode of the body region contact diode and an anode of the body diode are connected to the bipolar transistor. A first gate of the first MOS transistor is externally connected to a gate voltage of the IGBT power device and configured to control turning on and off of the first MOS transistor by means of the gate voltage of the IGBT power device. A second gate of the second MOS transistor is connected to an emitter voltage of the IGBT power device and configured to control turning on and off of the second MOS transistor by means of the emitter voltage of the IGBT power device.

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Jiangsu, China

Yuanlin Yuan