Shenzhen Pango Microsystems Co., Ltd.

Huawei Technologies Co., Limited

Yuanjun Liang

Kai Feng Li

Liang Zhang

Enbo Zhou

Tianjian Zuo

Guangyao You

Xinjian Chen

Chuntan Zhuo

The present invention provides a frequency selective circuit, comprising: a voltage-controlled oscillator for outputting a frequency corresponding to the frequency adjustment window; a frequency divider for dividing the clock frequency output by the voltage-controlled oscillator, and feeding back the resulting low frequency to the frequency selection unit; a frequency selective unit for comparing a reference frequency with the resulting low frequency output by the frequency divider, and providing the frequency adjustment window which is configured based on the frequency search window to the voltage-controlled oscillator; a register group for outputting the frequency search window which is provided to the frequency selective unit. The embodiment of the present invention convert the clock frequency from a high frequency to a low frequency. The low frequency is compared with the reference frequency to ultimately find the corresponding low frequency that has the same frequency as the reference frequency.

Frequency selection circuit

A high-speed sampling circuit is disclosed which comprises a sampling module for amplifying a differential input signal; a latch module for latching the differential output signal of the sampling module; a first control module for controlling the sampling module under a first clock signal; a second control module for controlling the latch module under a second clock signal; a third control module for controlling control the output of the differential output signal under the second clock signal. The high-speed sampling circuit of the disclosure, after sampling the differential input signal, the sampling module outputs it to the latch module and controls the latch module to output the differential output signal, compared to the existing two-stage sampling module, it saves the transmission delay of the two-stage sampling module and can improve the performance of the high-speed sampling band of the signal.

High speed sampling circuit

Disclosed are a clock and data recovery circuit, method and apparatus. The circuit comprises a receiving module for receiving an analog signal; a first equalization module connected to the receiving module, the first equalization module comprising a first totalizer and a second totalizer; a first sampling module connected to an output end of the first totalizer, the first sampling module comprising a first edge sampler and a second edge sampler that are connected to the output end of the first totalizer, respectively; a second sampling module connected to an output end of the second totalizer; a data processing module connected to both the first sampling module and the second sampling module; a clock recovery module connected to the data processing module; and an output module connected to the clock recovery module. In the present application, by means of the manner, a phase can be adjusted using a bias voltage, thereby accurately recovering clock information.

Clock and data recovery circuit, method and apparatus

A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.

Fixed time-delay circuit of high-speed interface

An optical signal processing method and a coherent receiver, wherein an in-phase signal XI in a first polarization direction and an in-phase signal YI in a second polarization direction are added up to obtain a signal I; a quadrature signal XQ in the first polarization direction and a quadrature signal YQ in the second polarization direction are added up to obtain a signal Q; and quantization, combination, and digital signal processing are performed on the I and the Q. After summation, two signals need to be quantized. Therefore, a quantity of ADCs is reduced by half. In addition, because power consumption of a summation component is less than that of an ADS, power consumption of optical signal processing can be reduced. In addition, because there is a preset value, the summation may be performed after phase-inversion is performed on one analog signal, thereby avoiding a signal loss caused by the summation.

Growing community of inventors

Shenzhen, China

Yuanjun Liang