University of Electronic Science and Technology of China

Other

Chengdu Sino Microelectronics Technology Co., Ltd.

Chengdu Huawei Electronic Technology Co., Ltd.

Yuanjun Cen

Jinda Yang

Hua Fan

Dagang Li

Daqian Hu

Franco Maloberti

Quanyuan Feng

Qiang Yu

Hadi Heidari

Chen Wang

Jian Luo

Dainan Zhang

Huaying Su

Xing Zhu

Jingxuan Yang

Jingtao Li

Peng Lei

Feixiang Xiang

Lang Feng

Xiaopeng Diao

Zhengbo Huang

Kelin Zhang

A high-speed high-linearity time-interleaved dynamic operational amplifier circuit includes a first current channel and a second current channel. The first current channel includes a first MOS transistor, a second MOS transistor and a third MOS transistor which are sequentially connected in series between a high level and a ground level. The first MOS transistor and the second MOS transistor have opposite conductivity types. A control end of the first MOS transistor is connected to a control end of the second MOS transistor. The second current channel includes a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor which are sequentially connected in series between the high level and the ground level. The fourth MOS transistor and the fifth MOS transistor have opposite conductivity types. A control end of the fourth MOS transistor is connected to a control end of the fifth MOS transistor.

High-speed high-linearity time-interleaved dynamic operational amplifier circuit

A high-frequency high-linear input buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a signal panning unit. A gate terminal of the first MOS transistor is used as an input terminal of the buffer. A current input terminal of the first MOS transistor is connected to a current output terminal of the second MOS transistor. A current output terminal of the first MOS transistor is connected to a current input terminal of the third MOS transistor. A current input terminal of the second MOS transistor is connected to a gate terminal of the third MOS transistor. An input terminal of the signal panning unit is connected to an input terminal of the buffer. An output terminal of the signal panning unit is connected to a gate terminal of the second MOS transistor. An output terminal of the third MOS transistor is connected to ground.

High-frequency high-linear input buffer differential circuit

The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.

Analogue-to-digital conversion method of pipelined analogue-to-digital converter and pipelined analogue-to-digital converter

Disclosed is a high-linearity low-voltage input buffer circuit. The buffer circuit includes main buffers of positive and negative input terminals comprised of NMOS transistor Mand Mas well as Mand M, auxiliary buffer comprised of PMOS transistors Mand Mas well as Mand M, replica current amplifier comprised of NMOS transistors Mand Mas well as Mand M. Two ends of a replica capacitor Cc are respectively connected with positive and negative output terminals of the auxiliary buffer. The auxiliary buffer is used to simulate a load effect of the main buffers to generate a replica current of a load current, then the replica current is mirrored to a load transistor of the main buffer by the current amplifier, and the load capacitor is charged and discharged through the load transistor.

High linearity and low voltage input buffer circuit

The disclosure belongs to the field of integrated circuit technologies, and particularly relates to a pipelined analog-to-digital converter capable of correcting capacitor mismatch and inter-stage gain errors. According to the disclosure, a PN code is injected into a digital domain or an analog domain of a pipelined sub-analog-to-digital converter, a mean value of codes outputted by a sub-analog-to-digital converter of an (i+1)pipeline stage in two cases that a PN code is equal to +1 and the PN code is equal to &#x2212;1 is counted under the condition that a code outputted by a sub-analog-to-digital converter of an ipipeline stage is b, and a capacitor mismatch error and an actual inter-stage gain of the ipipeline stage are estimated according to the mean value and a relationship between a capacitor mismatch error and an actual inter-stage gain error of a previous pipeline stage.

Pipelined analog-to-digital converter

A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors C*, C* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR ADC.

Method of calibrating capacitive array of successive approximation register analog-to-digital converter

A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C-C; and 4) selecting 64 groups of capacitors from Cto C, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.

Method for improving spurious free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) of capacitor-resistor combined successive approximation register (SAR) analog-to-digital converter (ADC) by capacitor re-configuration

A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.

Method of arranging capacitor array of successive approximation register analog-to-digital converter

Growing community of inventors

Chengdu, China

Yuanjun Cen