Cadence Design Systems, Inc.

Yuane Qiu

Xiaojun Wang

Judy Huckabay

Prasanti Uppaluri

Tianhao Zhang

Some embodiments provide a method for decomposing a region of an integrated circuit ('IC') design layout into multiple mask layouts. The method identifies a number of sets of geometries in the design layout region that must be collectively assigned to the multiple mask layouts. The method assigns the geometries in a first group of collectively-assigned sets to different mask layouts without splitting any of the geometries. The method assigns the geometries in a second group of the collectively-assigned sets to different mask layouts in such a way so as to minimize the number of splits in the geometries of the second group.

Growing community of inventors

Cupertino, CA, United States of America

Yuane Qiu