Qualcomm Incorporated

Yuancheng Christopher Pan

Junmou Zhang

Lew G Chua-Eoan

Zhi Zhu

Joon Hyung Chung

Xiongfei Meng

Hee Jun Park

Nan Chen

Christopher Kong Yee Chun

Ryan Michael Coutts

Chuang Zhang

Fifin Sweeney

Christopher Kong Chun

Jason Gonzalez

Managing power rails, including: a plurality of power rails, each power rail coupled to at least one power supply and configured to support a plurality of similarly-configured loads; and a power rail controller configured to merge and split the plurality of power rails based on total power consumption of the plurality of similarly-configured loads. The power rail management also determines the optimal power rail mode (merge/split) based on current load of each rail and adjusts the dynamic clock and voltage scaling policy, workload allocation on each core, and performance limit/throttling management according to the power rail mode.

Dynamic power rail control for clusters of loads

An apparatus including a conductive stack structure includes an Mlayer interconnect on an Mlayer and extending in a first direction on a first track, an Mlayer interconnect on an Mlayer in which the Mlayer is a lower layer than the Mlayer, a first via stack coupled between the Mlayer interconnect and the Mlayer interconnect, a second via stack coupled between the Mlayer interconnect and the Mlayer interconnect, a second Mlayer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mlayer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mlayer interconnect is between the second Mlayer interconnect and the third Mlayer interconnect. The second Mlayer interconnect and the third Mlayer interconnect are uncoupled to each other.

Via structure for optimizing signal porosity

A package substrate is provided that includes a substrate and a capacitor. The substrate comprises a cavity penetrating a core layer and metal layers of the substrate. The capacitor comprises electrode pads and is disposed in the cavity. One of the metal layers of the substrate includes a discontinuous metal plane, and the electrode pads directly contact the discontinuous metal plane.

Plane connected embedded substrate capacitor

Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.

Low power high resolution oscillator based voltage sensor

A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.

Integrated voltage regulator with embedded passive device(s) for a stacked IC

A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias.

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Saratoga, CA, United States of America

Yuancheng Christopher Pan