Boe Technology Group Co., Ltd.

Chongqing Boe Optoelectronics Technology Co., Ltd.

Google Inc.

Hefei Boe Optoelectronics Technology Co., Ltd.

Boe Technology Gropu Co., Ltd.

Yuanbo Zhang

Seungwoo Han

Seung Woo Han

Xing Yao

Jiayang Zhao

Wei Qin

Shuai Chen

Xiangxiang Zou

Zhuo Xu

Xiangye Xiao

Fan Yang

Guangliang Shang

Yajie Bai

Hanping Feng

Wenbo Li

Haoliang Zheng

Zhi Zhang

Heecheol Kim

Yujie Gao

Hailong Wu

Yun Sik Im

Xiaolin Wang

Ruoyu Ma

Liangyi Ou

Shijun Tian

Xue Dong

Wei Sun

Ming Jin Chen

Rui Wang

Xianjie Shao

Yunsik Im

Yan Yan

Mingfu Han

Honggang Gu

Yingmeng Miao

Xiuzhu Tang

Junsheng Chen

Zhihui Wang

Jaikwang Kim

Lijun Xiao

Xing Dong

Yonggang Wang

Tao Zhou

Lijun Xiong

Mi Zhang

Yoon Sung Um

Yan Fang

Qian Qian

Yan Xa Zhou

Yi Dan

Ming Deng

Peng Liang

Rui Xue

Jianing Lu

Zhihe Jin

Haipeng Zhu

Jian Zeng

Min Ran

Song Fu

Jungmok Jun

Robert S Jung

Pengyue Zhang

Zhulin Liu

Han-Seung- Woo

Ruiyi Chen

Baohua Liao

Yinfei Zhang

Zhe Su

Zhiheng Li

Han-Seung Woo

Haifeng Jin

Vincent Ngo Bao Khoi

Zijie Tang

Wenhao You

Jie Pan

The present disclosure provides a gate drive unit, a driving method thereof and a gate drive circuit. The gate drive unit includes a shift register and a plurality of output control modules. Each of the output control modules is connected to a corresponding clock scanning signal line and a corresponding first scanning signal output terminal, respectively. Each of the output control modules includes a first output control submodule and an output reset submodule. The first output control submodule is connected to a signal output terminal of the shift register, the corresponding clock scanning signal line and the corresponding first scanning signal output terminal, and configured to send a clock scanning signal of the corresponding clock scanning signal line to the corresponding first scanning signal output terminal, under control of a signal outputted by the signal output terminal of the shift register.

Gate drive unit and driving method thereof and gate drive circuit

A shift register circuit includes a first circuit, M second circuits, and N third circuits. M and N are both positive integers, N is an integer multiple of M, M is greater than or equal to 2, and a quotient of N and M is greater than or equal to 2. The first circuit includes a first signal output terminal. Each second circuit includes a second signal input terminal connected to the first signal output terminal. Each third circuit includes a third signal input terminal that is connected to one of second signal input terminals of the M second circuits. A second signal output terminal of each second circuit is connected to third signal input terminals of N/M third circuits, and different second signal output terminals are connected to different third signal input terminals.

Shift register circuit and driving method therefor, and gate drive circuit and display device

A Gate Driver on Array circuit and a driving method thereof, and a display device. The Gate Driver on Array circuit includes at least one group of shift registers, each group of shift registers includes a plurality of shift registers in cascade, the plurality of shift registers including a first shift register, a second shift register connected after the first shift register, and a third shift register connected after the second shift register, wherein the third shift register is provided with an initializing terminal connected to an output terminal of the first shift register.

Gate driver on array circuit and driving method thereof, and display device

A shift register unit includes a first output control circuit, a first output circuit, a second output control circuit, a second output circuit, a reset circuit, and a node set circuit. The node set circuit is configured to periodically transfer a first voltage having an inactive level to a first node within the shift register unit during being enabled.

Shift register unit, driving method thereof, gate drive circuit, and display device

A shift register includes a pull-up control circuit, a pull-up circuit, a pull-down control circuit, a pull-down circuit, and a reset circuit. The pull-down circuit is connected to the pull-down node, the pull-up node, a second control terminal, a first voltage terminal, and a signal output terminal, and is configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of the pull-down node; moreover, the pull-down circuit is further configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of a signal from the second control terminal.

Shift register and method of driving the same, gate driving circuit and display device

Embodiments of the present disclosure disclose a gate driving circuit, a method for driving the same, and a display apparatus. The gate driving circuit includes N stages of cascaded shift registers, N being an integer greater than or equal to 4. In the N stages of shift registers, an output signal terminal of an nstage of shift register is connected to an input signal terminal of an (n+I/2)stage of shift register, and a reset signal terminal of the nstage of shift register is connected to an output signal terminal of an (n+K)stage of shift register, wherein n is an integer greater than or equal to 1 and less than (N&#x2212;I/2), K is an integer greater than I/2 and less than I, and I is a number of clock signal lines connected to the gate driving circuit, which is an even number greater than or equal to 4.

Gate driving circuit, method for driving the same, and display apparatus

The present disclosure provides a display substrate such that each pixel unit of the display substrate includes a switching circuit and a control circuit, and the switching circuit is connected to a corresponding gate line, a control circuit of a respective pixel unit, and a corresponding pixel electrode. The control circuit is configured to transmit a data signal on a corresponding data line to a switching circuit of the respective pixel unit under control of a corresponding control signal line, and n is an integer not less than 2. The present disclosure further provides a display device including the above display substrate and a driving method for the above display substrate.

Display substrate, driving method thereof, display panel

The present disclosure relates to a touch display panel, a method and a device for driving the touch display panel. The method is applied to the touch display panel which includes L gate lines arranged sequentially and M touch scan lines arranged sequentially, where both L and M are positive integers larger than 1. The method includes dividing a duration for which the touch display panel displays each frame of image into N control time intervals with each of the N control time intervals including a display refresh time and a touch time arranged sequentially, where N is an integer larger than 1, during the duration for which the touch display panel displays each frame of image, driving the L gate lines sequentially in N display refresh times, and driving the M touch scan lines sequentially for K times in N touch times, where K is larger than 1.

Touch display panel and method for driving the touch display panel and device for driving the touch display panel

A shift register unit includes: a discharging TFT, a source electrode and a drain electrode of which are connected to a first low level signal input end and a pull-up node respectively; and a first discharging control unit connected to a gate electrode of the discharging TFT and configured to output a first control signal to the gate electrode of the discharging TFT between a first and a second time points, so as to enable the discharging TFT to be in an on state and output a first low level signal to the pull-up node, thereby to discharge the pull-up node. The first time point is a time point when the processing of a first frame by the shift register is ended, and the second time point is a time point when the processing of a second frame adjacent to the first frame by the shift register is started.

Shift register unit, shift register, display panel and display device

The present disclosure provides a GOA unit circuit, a method for driving the same, and a GOA circuit. The GOA unit circuit comprises a first input sub-circuit, a pull-up sub-circuit, a first pull-down sub-circuit, a reset sub-circuit, a second input sub-circuit, a noise control sub-circuit, a first de-noising sub-circuit, and a second de-noising sub-circuit. The first pull-down sub-circuit is connected to an output signal terminal, a first clock control signal terminal and a discharge signal terminal, a discharge signal provided by the discharge signal terminal is at a high level higher than that of an input signal provided by the input signal terminal, and the first pull-down sub-circuit is configured to discharge the output signal terminal under the control of the first clock control signal and the discharge signal, to pull down a potential at the output signal terminal to a low level. The GOA unit circuit is configured to drive gate lines of a display apparatus.

GOA unit circuits, methods for driving the same, and GOA circuits

A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

Supplement resetting module, gate driver circuit and display device

The present application relates to a gate drive unit circuit, comprising an input unit, an output unit, a pull-up node control unit, a pull-down node control unit and a pull-down unit. The input unit is used for transmitting a signal inputted by a first input signal terminal to a first node. The pull-up node control unit is used for transmitting a signal inputted by a first voltage terminal or a second voltage terminal to a pull-up node. The output unit is used for transmitting a signal inputted by a first control signal terminal to an output signal terminal. The pull-down node control unit is used for transmitting the input inputted by the first voltage terminal or the second voltage terminal to a pull-down node. The pull-down unit is used for transmitting a signal inputted by the second voltage terminal to the output signal terminal.

Gate drive unit circuit, gate drive circuit, display device and driving method

Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.

Shift register unit, gate driving circuit and driving method thereof, and display apparatus

An inverter and a method for driving the inverter, a gate driver on array (GOA) unit, a GOA circuit and a display device relate to a technical field of display, and are proposed to supply stable inverter output signal. The inverter comprises a control module and an output module. The control module is configured to control a voltage at a control node under the control of a first clock signal at a first clock signal terminal, a second clock signal at a second clock signal terminal, an input signal at an input terminal and voltages at a first level terminal and a second level terminal. The output module is configured to set a voltage at the output terminal to the voltage at the first level terminal or the voltage at the second level terminal under the control of the control node and the input signal at the input terminal.

Inverter and method for driving the inverter, gate on array unit and gate on array circuit

In one example, a computing device includes at least one processor configured to output for display, a graphical keyboard. The at least one processor may also be configured to model, in a first lattice, a plurality of candidate character strings that include symbols of a first alphabet. The first lattice may indicate spatial probabilities of the plurality of candidate character strings. The at least one processor may be configured to determine, using a second lattice that indicates probabilities of one or more words of a second language based at least in part on the spatial probabilities of the plurality of candidate character strings, a probability that the at least one of the plurality of candidate character strings corresponds to at least one word included in the second language. The at least one processor may be configured to output for display, the one or more symbols representing at least one word.

Virtual keyboard input for international languages

Growing community of inventors

Beijing, China

Yuanbo Zhang