Future Wei Technologies, Inc.

Nokia Corporation

Huawei Technologies Co., Limited

Yuanbin Guo

Joseph R Cavallaro

Weizhong Chen

Tong Sun

Dennis McCain

Jianzhong Zhang

Giridhar Dhati Mandyam

Yang Sun

Kiarash Amiri

Hoang Nguyen

Bei Yin

Zhikun Cheng

Joe Dowling

Guohui Wang

Junhong Nie

An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a 'one' bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.

System and method for a floating-point format for digital signal processors

An embodiment method for network communications includes receiving, by a network device, a plurality of channel quality indicator (CQI) symbols and one or more acknowledgement (ACK) symbols and selecting a reduced set of candidate CQI symbols by comparing a plurality of candidate CQI symbols with the plurality of CQI symbols. The method further includes generating a plurality of candidate CQI and ACK symbol combinations by combining the reduced set of candidate CQI symbols with candidate ACK symbols. The network device detects the plurality of CQI symbols and the one or more ACK symbols by comparing the plurality of candidate CQI and ACK symbol combinations with the plurality of CQI symbols and the one or more ACK symbols.

System and method for channel quality indicator and acknowledgement joint detection

An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.

System and method for signal processing in digital signal processors

According to one embodiment, an apparatus includes a digital signal processor configured to perform a multiple antenna detection portion of a baseband signal processing process using a first floating point processing unit, and perform all other portions of the baseband signal processing process using a half-precision floating point processing unit. The first floating point processing unit has a bit width that is larger than the bit width of the half-precision floating point processing unit.

Efficient baseband signal processing system and method

A wireless receiver is constructed to equalize a time-domain received signal, detect a plurality of symbols of the equalized time-domain received signal, and perform interference cancellation on the time-domain received signal. The interference cancellation can be performed using a partial result produced by an IDFT, and may use only neighboring symbols in a detected plurality of symbols. The resulting wireless receiver can be constructed to operate efficiently under a plurality of wireless standards.

Method and device for inter-chip and inter-antenna interference cancellation

A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.

System and method for contention-free memory access

A system, apparatus and method for a multi-stage Parallel Residue Compensation (PRC) receiver for enhanced suppression of the Multiple Access Interference (MAI) in Code Division Multiple Access (CDMA) systems. The accuracy of the interference estimation is improved with a set of weights computed from an adaptive Normalized Least Mean Square (NLMS) algorithm. In order to reduce complexity, the commonality of the multi-code processing is extracted and used to derive a structure of PRC to avoid direct interference cancellation. The derived PRC structure reduces the interference cancellation architecture from a complexity that is proportional to the square of the number of users to a complexity that is linear with respect to the number of users. The complexity is further reduced by replacing dedicated multiplier circuits with simple combinational logic.

System, apparatus, and method for adaptive weighted interference cancellation using parallel residue compensation

Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size N&#xd7;N with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2&#xd7;2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4&#xd7;4 matrices are partitioned into 2&#xd7;2 block sub-matrices, inverted, and rebuilt into a 4&#xd7;4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.

Reduced parallel and pipelined high-order MIMO LMMSE receiver architecture

A receiver, such as a CDMA MIMO receiver, includes a LMMSE-based chip-level equalizer constructed so as to implement a FFT accelerated iterative algorithm having a complexity of order O(N log(N)), where N is the dimension of a covariance matrix. The equalizer uses one of an overlap-save or an over-lap add FFT architecture.

FFT accelerated iterative MIMO equalizer receiver architecture

Receiving downlink CDMA signals in a fast-fading environment is facilitated at higher receiver velocities by updating the block-adaptive linear minimum mean square error (LMMSE) downlink CDMA equalizer. The autocorrelation matrix of the observed data is updated by passing block-wise autocorrelation slides through a filter. Each autocorrelation slide is an autocorrelation matrix estimated from a short block of observed data over which the channel can be considered constant. This method achieves a reliable estimate for the autocorrelation matrix when the block size must be small to ensure that the block-wise stationarity assumption holds in cases of fast fading channels. In addition, small block sizes make it possible to satisfy the equalizer delay constraint imposed by hardware and certain voice transmission standards such as CDMA2000 1X where demodulated data must be delivered within only several symbol periods of the signal arrival time.

Weighted autocorrelation method for downlink CDMA LMMSE equalizers

In the reception of a downlink MIMO CDMA signal, the receiving unit performs a simplified process of linear equalization that eliminates the need for inverting the correlation matrix. The correlation matrix is approximated to a good degree by a circulation matrix that is diagonalized by FFT operations, thus substituting two FFTs and one IFFT having a complexity of for the direct matrix inversion having a complexity of O(L).

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Allen, TX, United States of America

Yuanbin Guo