Taiwan Semiconductor Manufacturing Comp. Ltd.

Yuan-Yao Chang

Min-Tar Liu

Jing-Sen Wang

Ming-Da Cheng

Ching-Wen Hsiao

Pei-Hsuan Lee

Shang-Wei Fang

Hsiao-Wen Chung

Shan-Yu Huang

Ting-Hua Hsieh

Yu-Hsuan Huang

Meng-Hsiu Hsieh

Shuo-Wen Chang

Yu-Hsien Li

Li-Chun Hung

Wei-Ray Lin

Chien-Chang Lee

Chu Fu Chen

Huan Chi Tseng

Chia-Chia Kan

Chia-Wei Huang

Wei-Jhih Wang

Tseng-Chin Lo

Kuo-Chuan Chang

Tseng Chin Luo

Chia Wei Huang

Hung-Chi Chiu

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is in direct contact with the first conductive line, and a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Chip structure with conductive pillar and method for forming the same

One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

System and method for measuring device inside through-silicon via surroundings

The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (V) to the gate electrode to turn on the first transistor, determining a first threshold voltage (V) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (V); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.

Semiconductor device and analyzing method thereof

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Chip structure and method for forming the same

A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

Overlay error and process window metrology

A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.

Method, test line and system for detecting semiconductor wafer defects

One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements.

Multidirectional semiconductor arrangement testing

A method of measuring a parameter of a device in a circuit includes providing a device under test (DUT). The DUT includes a metal oxide semiconductor (MOS) transistor having a gate, a source, and a drain coupled to a first voltage supply node. The method further includes coupling a constant current source to the source of the transistor, coupling an operational amplifier to the transistor, and measuring a parameter of the transistor.

Method and apparatus for device parameter measurement

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Kaohsiung, Taiwan

Yuan-Yao Chang