Lsi Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Hgst Netherlands, B.v.

Yuan Xing Lee

Shaohua Yang

George Mathew

Hongwei Song

Weijun Tan

Hao Zhong

Zongwang Li

Richard Leo Galbraith

Yang Han

Travis Roger Oenning

Richard Rauschmayer

Jongseung Park

Changyou Xu

Ksenija Lakovic

Bruce Alexander Wilson

Mario Blaum

Jeffrey Paul Grundvig

Jingfeng Liu

Hideki Sawaguchi

Kelly K Fitzpatrick

Ivana Djurdjevic

Harley Burger

Erich Franz Haratsch

Kiran Kumar Gunnam

Viswanath Annampedu

Jefferson E Singleton

Kapil Gaba

Evangelos Stavros Eleftheriou

Roy Daron Cideciyan

Ming Jin

Weldon Mark Hanson

Nenad Miladinovic

Morishi Izumita

Nils Graef

Scott M Dziak

Lingyan Sun

Li Du

Madhusudan Kalluri

Suharli Tedja

Robert Alan Greene

Weining Zeng

Fuminori Sai

Ching-Fu Wu

Liu Jingfeng

Sizhen Yang

Ismail Demirkan

David L Parker

Jonseung Park

Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium having servo data thereon. A read/write head assembly is disposed in relation to the storage medium. A servo based fly-height adjustment circuit receives the servo data via the read/write head assembly, and calculates a first harmonics ratio based on the received data and compares the first harmonics ratio with a second harmonics ratio to determine an error in the distance between the read/write head assembly and the storage medium.

Systems and methods for fly-height control using servo data

Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses a storage medium that includes a N&#xd7;Ndata pattern. The N&#xd7;Ndata pattern includes Nbits repeated Ntimes. Both Nand Nare each greater than one. The methods further include performing an initial read of the N&#xd7;Ndata pattern, which is stored to a first register. Nsubsequent reads of the N&#xd7;Ndata pattern are each processed by: performing a subsequent read of the N&#xd7;Ndata pattern, and performing a difference calculation using the initial read of the N&#xd7;Ndata pattern and the subsequent read of the N&#xd7;Ndata pattern and resulting in the calculation of a difference vector that is stored to a second register; and performing a difference accumulation calculation to generate an accumulation vector which is stored to a third register. Based at least in part on the stored N&#xd7;Ndata pattern and the stored difference vector, an electronics noise power is calculated.

Systems and methods for memory efficient signal and noise estimation

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, and an inter-track interference signal estimator circuit. The data buffer is operable to store a previous track data set. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set.

Systems and methods for inter-track interference compensation

Various embodiments of the present invention provide systems and methods for estimating noise components in a received signal set. For example, one embodiment of the present invention provides a noise estimation circuit that includes a data detector circuit and a noise component calculation circuit. The data detector circuit receives a series of data samples and provides a detected output, and the noise component calculation circuit provides an electronics noise power output and a media noise power output each calculated based at least in part on the detected output and the series of data samples.

Systems and methods for determining noise components in a signal set

Various embodiments of the present invention provide systems and methods for deriving data from a defective media region. As an example, a method for deriving data from a defective media region is disclosed that includes providing a storage medium and performing a media defect detection that indicates a defective region on the storage medium. A first data decode is performed on data corresponding to the defective region. The first data decode yields a first output. It is determined that the first output failed to converge and based at least in part on the failure of the first output to converge, a second data decode is performed on the data corresponding to the defective region. The second data decode includes zeroing out any soft data corresponding to the defective region and providing a second output.

Systems and methods for multilevel media defect detection

Methods and apparatus are provided for detection of a synchronization mark based on a position of an extreme distance metric. A synchronization mark is detected in a received signal by computing a distance metric between the received signal and an ideal version of the received signal expected when reading the synchronization mark, wherein the distance metric is computed for a plurality of positions within a search window; determining a substantially extreme distance metric within the search window; and detecting the synchronization mark based on a position of the substantially extreme distance metric. The distance metric can comprise a sum of square differences or a Euclidean distance between the received signal and the ideal version of the received signal.

Methods and apparatus for synchronization mark detection based on a position of an extreme distance metric

Various embodiments of the present invention provide systems and methods for updating detector parameters in a data processing circuit. For example, a data processing circuit is disclosed that includes a first detector circuit, a second detector circuit, and a calibration circuit. The first detector circuit is operable to receive a first data set and to apply a data detection algorithm to the first data set, and the second detector circuit is operable to receive a second data set and to apply the data detection algorithm to the second data set. The calibration circuit is operable to calculate a data detection parameter based upon a third data set. The data detection parameter is used by the first detector circuit in applying the data detection algorithm to the first data set during a period that the data detection parameter is used by the second detector circuit in applying the data detection algorithm to the second data set.

Systems and methods for updating detector parameters in a data processing circuit

Various embodiments of the present invention provide systems and methods for variable iteration data processing.

Systems and methods for queue based data detection and decoding

Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving a codeword that has at least a first circulant with a plurality of data bits and a first circulant parity bit, a second circulant with a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits. The methods further include decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, performing a first circulant parity check on the first circulant, and performing a second circulant parity check on the second circulant.

Systems and methods for utilizing circulant parity in a data processing system

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge.

Systems and methods for hard decision assisted decoding

Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.

Decoding techniques for correcting errors using soft information

Various embodiments of the present invention provide systems and methods for out of order memory management. For example, a method for out of order data processing is disclosed. The method includes providing an out of order codeword memory circuit that includes a number of codeword memory locations in a codeword memory area and the same number of index values in an index area. Each of the index values corresponds to a respective one of the codeword memory locations. The methods further include receiving a data set; storing the data set to one of the codeword memory locations; receiving an indication that the data set stored in the one of the codeword memory locations has completed processing; and grouping an index value corresponding to the one of the codeword memory locations with one or more other index values corresponding to unused codeword memory locations.

Systems and methods for out of order Y-sample memory management

Various embodiments of the present invention provide systems and methods for phase offset based spectral aliasing compensation. For example, a circuit for spectral aliasing reduction is disclosed that includes a phase shift circuit operable to phase shift an analog input signal and to provide a phase shifted analog signal; a first analog to digital converter circuit operable to provide a first series of digital samples corresponding to the analog input signal at a sampling frequency; a second analog to digital converter circuit operable to provide a second series of digital samples corresponding to the phase shifted analog signal at the sampling frequency; and an averaging circuit operable to average the first series of digital samples with the second series of digital samples to yield an average output.

Systems and methods for phase offset based spectral aliasing compensation

Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information.

Techniques for correcting errors using iterative decoding

Various approaches related to systems and methods for LDPC based data processing.

Systems and methods for quasi-cyclic LDPC code production and decoding

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San Jose, CA, United States of America

Yuan Xing Lee