Dialog Semiconductor (uk) Limited

Amazing Microelectronic Corporation

Richtek Technology Corporation

United Microelectronics Corp.

National Yang Ming Chiao Tung University

Faraday Technology Corporation

Amazing Microelectronics Corp.

Yuan-Wen Hsiao

Ming-Dou Ker

Ryan Hsin-Chin Jiang

Jian-Rong Huang

Chi-Chia Huang

Yu-Ta Lin

Chang-Tzu Wang

Hsin-Chin Jiang

Yi-Cheng Wan

Chien-Hui Wang

Yuh-Kuang Tseng

Yu-Lun Chang

Adaptive-on-time techniques to improve the frequency variations inherent in constant-on-time COT converters are presented. A switching converter contains a power switch; a pulse generator adapted to generate a pulsed signal to switch the power switch on with a switching frequency; a ramp generator adapted to generate a ramp signal; and a controller adapted to detect a parameter of the ramp signal, compare the parameter with a reference value, and to generate a control signal based on the comparison to control the switching frequency. This allows controlling a switching frequency of the converter without increasing a noise level of the converter.

Adaptive on-time switching converter

A switching converter comprising a regulation circuit adapted to regulate an output value of the converter based on a ramp signal is provided. A feedback circuit adapted to control at least one of a delay and a slope of the ramp signal based on a parameter of the ramp signal is also provided. A method of regulating an output value of a switching converter is also presented.

Switching converter with ramp-based output regulation

A switching converter, which produces an output voltage, contains a switch operable between a first state for opposing a decrease in the output voltage and a second state for opposing an increase in the output voltage. The converter also contains a circuit adapted to determine a time period during which the output voltage is decreasing, wherein during the time period the switch is in the first state. The circuit also calculates, based on the time period, a time to turn the switch from the first state to the second state to prevent the output voltage increasing above a reference value. Optionally, the time to turn the switch to the second state is based on a duty cycle of the converter.

Switching converter with improved recovery time

A voltage converter controller, adapted to a voltage converter circuit, includes a power switch controller and a dead-time determining circuit. The power switch controller receives a PWM signal and outputs a high-side control signal and a low-side control signal accordingly to control the conduction and cut-off of a high-side power switch and a low-side power switch respectively. When the power switch controller starts to control the low-side power switch cut-off, after a first dead-time, the power switch controller starts to control the high-side power switch conducting. The dead-time determining circuit detects a current of the low-side power switch to be larger or smaller than a threshold current when the low-side power switch is conducted, and determines the first dead-time to be a first value or a second value accordingly.

Voltage converter controller and voltage converter circuit

The present invention provides a multi-phase switching regulator and a droop circuit for use in the multi-phase switching regulator. The multi-phase switching regulator generates pulse width modulation (PWM) signals according to an output voltage and a droop signal, to drive a plurality of switching sets to convert an input voltage to the output voltage. The droop circuit detects the sum of the currents generated by the plurality of switching sets and provides the droop signal which is related to the sum of the currents to the multi-phase switching regulator. The droop signal can be used for over current protection (OCP) or for the droop control.

Multi-phase switching regulator and droop circuit therefor

An ESD protection circuit for a differential I/O pair is provided. The circuit includes an ESD detection circuit, a discharge device, and four diodes. The first diode is coupled between the first I/O pin and the discharge device in a forward direction toward the discharge device. The second diode is coupled between the second I/O pin and the discharge device in a forward direction toward the second I/O pin. The third diode is coupled between the discharge device and the positive power line in a forward direction toward the positive power line. The fourth diode is coupled between the discharge device and the negative power line in a forward direction toward the discharge device. Via an output end, the ESD detection circuit triggers the discharge device during ESD events.

ESD protection circuit for differential I/O pair

An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

ESD protection circuit with active triggering

An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first Ndiffusion region, a first Pdiffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second Ndiffusion region electrically connected to the first Pdiffusion region, a second Pdiffusion region electrically connected to the first Ndiffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.

Electrostatic discharge protection device and related circuit

An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.

ESD protection circuit for IC with separated power domains

The present invention discloses a bonding pad structure disposed in a semiconductor device and a method for forming the bonding pad structure. The semiconductor device includes a substrate. The bonding pad structure includes a connection structure and an induction structure. The connection structure allows for a direct connection with a bonding wire. The induction structure is coupled with the connection structure and lowers an effective capacitance between the bonding wire and the substrate.

Growing community of inventors

Taichung, Taiwan

Yuan-Wen Hsiao