International Business Machines Corporation

Yuan Taur

Hon-Sum Philip Wong

Hussein Ibrahim Hanafi

Diane Catherine Boyd

William C Wille

Stuart M Burns

Jack Allan Mandelman

Louis L Hsu

Guy M Cohen

Kevin K Chan

Jack Oon Chu

Yuan-Chen Sun

Devendra K Sadana

Ghavam G Shahidi

Jian J Xu

Barbara A Chappell

Burn J Lin

Bijan Davari

Denny D Tang

Hsing-Jen C Wann

George A Sai-Halasz

Heemyong Park

A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.

Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques

Field effect transistors with vertical gate side walls and method for making such transistors

A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10&deg; to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for providing source/drain extensions or halo doping or both.

Forming steep lateral doping distribution at source/drain junctions

Metal oxide semiconductor field effect transistor (MOSFET) including a drain region and a source region adjacent to a channel region. A gate oxide is situated on the channel region and a gate conductor with vertical side walls is placed on the gate oxide. The MOSFET further includes a threshold adjust implant region and/or punch through implant region being aligned with respect to the gate conductor and limited to an area underneath the gate conductor. Such a MOSFET can be made using the following method: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack having the lateral size and shape of a gate hole to be formed; defining the gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; implanting threshold adjust dopants and/or punch through dopants through the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering portions of the semiconductor structure surrounding the gate hole; and removing at least part of the dielectric stack.

Field effect transistors with improved implants and method for making

A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.

Method for making field effect transistors having sub-lithographic gates

A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.

Vertical double-gate field effect transistor

An integrated circuit is described incorporating a substrate, a layer of insulator, a layer of silicon having raised mesas and thin regions therebetween to provide ohmic conduction between mesas, electronic devices on the mesas, and interconnection wiring. The invention overcomes the problem of a floating gate due to charge accumulation below the channel of MOS FET's.

SOI CMOS structure

A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g., polysilicon) such that top and bottom gates are self-aligned to each other and to the channel region. Also disclosed is a self-aligned double-gate MOSFET constructed in accordance with the foregoing method.

Method for fabricating a self-aligned double-gate MOSFET by selective

Self-aligned double-gate MOSFET by selective lateral epitaxy

A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are formed over regions of oxide adjacent the doped regions. A planarized insulator is formed between the gate stacks. Openings are provided in the planarized insulator for contacts to the doped regions and the gate stacks. Conductive material fills the openings to form contacts for the doped regions and for the gate stacks. A patterned layer of conductive material on the planarized insulator connects selected ones of the contacts for wiring portions of the latch. A six device SRAM cell comprises a deep isolation trench formed in the substrate; a first latch including two transistors formed of p-type material on a first side of the trench; a second latch including two transistors formed of n-type material on a second side of the trench opposite the first side of the trench, and connection means for electrically cross wiring the transistors of the first latch to the transistors of the second latch. In forming the latch a self-aligned process for separately forming contacts to diffusion regions and gate stacks on the semiconductor substrate is used.

SRAM cell with capacitor

A silicon-on-insulator lateral bipolar transistor having an edge-strapped base contact is disclosed. A thin layer of oxide is deposited on a silicon-on-insulator structure and a layer of polysilicon is deposited on the thin oxide layer that is patterned and etched to form an extrinsic base region of the transistor. The polysilicon extrinsic base is very heavily doped and the thin oxide layer acts as both a diffusion stop and an etch stop during the formation of the extrinsic base. A silicon edge contact region is formed of selective epitaxy or polysilicon to connect the extrinsic base to the intrinsic base formed in the silicon-on-insulator layer.

SOI lateral bipolar transistor with edge-strapped base contact and

A system for evaluating and measuring the performance of lithographic structures, and more particularly for monitoring the optical parameters of a projection lithography system which uses the instant electrical readout from an array of photosensitive detectors fabricated on a silicon wafer in combination with a computer for real-time characterization of lithographic devices and the evaluation of optical E-beam, ion-beam and X-ray parameters. The system includes a source radiation, such as a source of ultraviolet light, a projection mask which masks the illumination from the source. The illumination is then directed through a projection lens onto a semiconductor wafer mounted on an x-y stepping table. A standard digital data processor is provided to control the x-y drive mechanism for the stepping table. The computer also controls a Z drive mechanism for movement in a vertical direction. The semiconductor wafer contains a plurality of radiation detectors which are responsive to the radiation from the source. These detectors use a conventional power supply controlled by the computer, and employ an output signal means which obtains the radiation produced output signals from the detectors and applies them to the computer. The use of a unique mask with the radiation-sensitive detectors is employed in combination with compiling means for the purposes of evaluating image projection from a lithographic system, including the properties of intensity, modulation transfer function (MTF), focus and alignment.

System for real-time monitoring the characteristics, variations and

A process for forming self-aligned complementary n.sup.+ and p.sup.+ source/drain regions in CMOS structures using a single resist pattern as a mask to form both the n.sup.+ channel implant and then the p.sup.+ channel implant. The resist pattern is formed using conventional lithography techniques to form an implant mask which covers the p.sup.+ channel region while the n.sup.+ source and drain regions are ion implanted. The resist mask is then used as a lift-off mask in order to cover the n.sup.+ channel region while the p.sup.+ source and drain regions are ion implanted.

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Bedford, NY, United States of America

Yuan Taur