Advanced Micro Devices Corporation

Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.

Eon Silicon Devices, Inc.

Hyundai Electronics America, Inc.

Edn Silicon Devices, Inc.

Wuhan Xinxin Semiconductor Manufacturing Co., Ld.

Yuan Tang

Jen-Tai Hsu

Jian Feng Chen

Chi K Chang

James C Yu

Hsingya Arthur Wang

Chung K Chang

Lee Edward Cleveland

Ming Sang Kwan

Scott D Luning

Michael Allen Van Buskirk

David K Liu

Chien-Sheng Su

James Juen Hsu

Salvatore F Cagnina

Bin Sheng

Zhifeng Mao

Yi Xu

Haike Dong

Mark T Ramsbey

Peter Rabkin

Sameer S Haddad

Nancy S Leong

Tiao-Hua Kuo

Jein-Chen Young

Michael David Fliesler

Jonathan S Su

Qimeng Zhou

Kenneth Miu

Yi Luo

Shengbo Zhang

Shengwen Luan

Hung-Yu Chang

Aaron Yip

Shiou-Yu Alex Wang

Sean Chen

Byoung Kwon Cha

Jeffrey W Anthony

An oscillator including two sequentially connected pulse generation circuits is disclosed. Each pulse generation circuit includes a charge/discharge circuit and a switch circuit and outputs a first or second signal depending on an input signal. The switch circuit controls the charge/discharge circuit so that the latter is charged when the input signal is at a first level and discharged when the input signal is at a second level higher than the first level. When the input signal is at the first level, the first signal is at the first level and the second signal is at the second level. When the input signal is at the second level, the first signal is at the second level and the second signal is at the first level. Upon completion of discharge of the charge/discharge circuit, the first signal changes to the first level and the second signal changes to the second level.

Oscillator

A charge pump drive circuit is disclosed. The charge pump drive circuit provides a switch signal to a charge pump which provides a memory with a read voltage and a read current. The charge pump drive circuit includes a read drive circuit and a standby drive circuit. The read drive circuit is powered by a first power supply and provides the charge pump with a switch signal when the memory is in an active reading state. The standby drive circuit is powered by a second power supply and provides the charge pump with a switch signal when the memory is in a read standby state. The first power supply provides a voltage level ranging from 1.6 V to 3.8 V, and the second power supply provides a voltage level of 1.5 V.

Charge pump drive circuit with two switch signals

A local X-decoder for a memory system including a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and a voltage clamping transistor coupled to the decoding unit, and configured to reduce a voltage difference across a global word line signal and the word line signal by an amount of a threshold voltage of the voltage clamping transistor.

Local X-decoder and related memory system with a voltage clamping transistor

A band-gap reference circuit including a low drop-out (LDO) regulator and a reference circuit is disclosed. The LDO regulator outputs a regulating voltage which is provided to the reference circuit, and wherein the regulating voltage is maintained constant and powers the reference circuit such that the reference circuit outputs a band-gap reference voltage. According to the reference circuitry, the LDO regulator can output a stable voltage such that the regulating voltage can be maintained constant, therefore, causing the band-gap reference voltage output from the reference circuit to be maintained constant, hence improving the reliability of the band-gap reference voltage.

Band-gap reference circuit

A band-gap reference circuit including a charge pump circuit and a reference circuit is disclosed. The charge pump circuit is powered by a supply voltage and thereby outputs a regulating voltage which is higher than the supply voltage and powers the reference circuit such that the reference circuit outputs a band-gap reference voltage. Powering the reference circuit with the regulating voltage that is made higher than the supply voltage by the charge pump circuit enables 1) normal operation of the band-gap reference circuit at the supply voltage that is lower than a lowest voltage required by the band-gap reference circuit; and 2) minimization (almost elimination) of fluctuations in the regulating voltage output from the charge pump circuit and hence a stable and more accurate band-gap reference voltage output from the band-gap reference circuit.

A voltage detection circuit for a charge pump is disclosed. The voltage detection circuit includes a sampling circuit and a latch circuit. The sampling circuit is configured to sample a supply voltage and provide the latch circuit with a sampled voltage. The latch circuit is configured to detect the sampled voltage and latch a result of the detection. And the latch circuit is connected to a voltage regulation circuit which is configured to regulate a charge-pump cascade structure in the charge pump based on the result of the detection so as to maintain an output voltage of the charge pump stable.

Voltage detection circuit for charge pump

A charge pump drive circuit is disclosed. The charge pump drive circuit includes a first pulse generating circuit and a second pulse generating circuit. Each of the first pulse generating circuit and the second pulse generating circuit is configured to connect to a charge pump. The first pulse generating circuit is configured to provide the charge pump with a series of first pulse signals. The second pulse generating circuit is configured to generate a second pulse signal in response to and based on an address translation detection signal and provide the second pulse signal to the charge pump or to the first pulse generating circuit. The first pulse generating circuit generates an additional first pulse signals based on the second pulse signal.

Charge pump drive circuit

A circuit for regulating a leakage current in a charge pump is disclosed. The circuit includes a bias voltage generating circuit and a first transistor, wherein: the bias voltage generating circuit generates a bias voltage that is proportional to a supply voltage; a gate of the first transistor is coupled to the bias voltage; the first transistor has a drain that is coupled to an output of the charge pump and a source that is grounded; a voltage the drain of the first transistor is proportional to the supply voltage; and a current flowing through the source and drain of the first transistor is proportional to the supply voltage that powers the charge pump.

Circuit for regulating leakage current in charge pump

A sensing circuit includes a plurality of cascode transistors including: a Flash memory cell; a sensing node; and an NMOS. The sensing circuit further includes a charge pump for generating an output voltage. A first output voltage is directly input to the plurality of cascode transistors during programming, and a second output voltage of the charge pump is coupled to a gate of the NMOS during a read to bias the NMOS. A sensing amplifier has an input coupled to the sensing node for receiving read data of the Flash memory cell when the NMOS is biased. A low-pass filter is coupled between the second output voltage of the charge pump and the gate of the NMOS.

Removing pump noise in a sensing circuit

A voltage regulator includes a first feedback loop and a second feedback loop. The first feedback loop includes a charge pump outputting a first output voltage, a first transistor ladder and a control circuit. The first transistor ladder divides the first output voltage to generate a first feedback voltage. The control circuit receives the first feedback voltage and controls a level of the first output voltage according to the first feedback voltage and a reference voltage. The second feedback loop includes a power transistor, a second transistor ladder and an operational amplifier. The power transistor receives the first output voltage to output a second output voltage. The second transistor ladder divides the second output voltage to generate a second feedback voltage. The operational amplifier outputs a control signal to the power transistor by receiving the second feedback voltage and a reference voltage selected from one of a plurality of levels.

Voltage regulator with flexible output voltage

A two-sided memory array is disclosed. Each side includes four local x-decoders. Each local x-decoder includes: a first pair of cascode transistors coupled to a first signal; a second pair of cascode transistors coupled to the first signal, a second signal, and a word line; a third transistor coupled to the first signal; and a third pair of cascode transistors coupled to the second signal, a third signal, and the word line. All transistors in each local x-decoder are disposed vertically, and P-channels and N-channels on each side of the memory array are disposed in an order corresponding to P-channels of a first local x-decoder, P-channels of a second local x-decoder, P-channels of a third local x-decoder, P-channels of a fourth local x-decoder, N-channels of the fourth local x-decoder, N-channels of the third local x-decoder, N-channels of the second local x-decoder and N-channels of the first local x-decoder.

Layout structure of local x-decoder

A local X-decoder for a memory system includes a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and an unselected erase detecting unit coupled to the decoding unit, and configured to increase an absolute voltage coupled to the word line signal from a well of the memory cell according to an unselected erase mode signal generated by an erase mode decoder of the memory system; wherein the word line signal is floating to a same level as the well of the memory cell when the memory cell is unselected in an erase mode of the memory system.

Local x-decoder and related memory system

A low drop-out (LDO) regulator including a first operational amplifier, a first transistor, a second transistor, a voltage feedback circuit and a charge pump is disclosed. Each of the first transistor and the second transistor is coupled between supply voltage and an output voltage. The first operational amplifier outputs a first gate-controlled voltage to turn the first transistor on or off. A second gate-controlled voltage is provided to the second transistor to turn it on or off. The charge pump makes the second gate-controlled voltage equal to the sum of the output voltage, a threshold voltage of the second transistor and a drive voltage of the second transistor. The voltage feedback circuit provides a feedback voltage to the first operational amplifier. The first gate-controlled voltage is positively correlated to the feedback voltage. The first transistor is a P-channel field effect transistor; the second transistor is an N-channel field effect transistor.

Low drop-out regulator

A charge pump system includes: a differential amplifier, for receiving a feedback voltage and a reference voltage and generating an output signal; an oscillating circuit for generating clock pulses; a charge pump for receiving the clock pulses and generating an output voltage; a current sink coupled to the output of the charge pump; a first pair of cascode transistors for generating a digital signal; and an inverter for inverting the digital signal to generate a first digital signal according to the output signal, wherein the first digital signal is input to the current sink. When the feedback voltage is higher than the reference voltage, the first digital signal will be generated and the current sink will be turned on, and when the feedback voltage is lower than the reference voltage, the first digital signal will not be generated and the current sink will be turned off.

Digital control of charge pump

A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characteristics (e.g. transistor cell channel length) exhibit tighter program rate distributions than for the same arrays in which drain side programming is used.

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San Jose, CA, United States of America

Yuan Tang