Taiwan Semiconductor Manufacturing Comp. Ltd.

Yuan-Shun Chao

Hou-Yu Chen

Chih-Wei Kuo

Shyh-Horng Yang

Chien-Hao Chen

Cheng-Lung Hung

Chao-Hsuing Chen

Yong-Tian Hou

Chie-Iuan Lin

Kuo Lung Li

Chih-Pin Tsao

A semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer, a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction, and a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer. The source/drain structure includes a SiP layer, and an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.

Integrated circuit metal gate structure

A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.

Multi-gate devices with replaced-channels and methods for forming the same

In a method of manufacturing a semiconductor device, a first layer containing a SiGelayer doped with phosphorous is formed over an n-type semiconductor layer, a metal layer containing a metal material is formed over the first layer, and a thermal process is performed to form an alloy layer including Si, Ge and the metal material.

Semiconductor device and manufacturing method thereof by forming thin uniform silicide on epitaxial source/drain structure

A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. The fin structure has a top surface and side surfaces and the top surface is located at a height Hmeasured from the substrate. An insulating layer is formed over the fin structure and the substrate. In the first recessing, the insulating layer is recessed to a height Tfrom the substrate, so that an upper portion of the fin structure is exposed from the insulating layer. A semiconductor layer is formed over the exposed upper portion. After forming the semiconductor layer, in the second recessing, the insulating layer is recessed to a height Tfrom the substrate, so that a middle portion of the fin structure is exposed from the insulating layer. A gate structure is formed over the upper portion with the semiconductor layer and the exposed middle portion of the fin structure.

Semiconductor device including fin structures and manufacturing method thereof

In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.

A FinFET device and a method for fabricating a FinFET device are disclosed. An exemplary method of fabricating a FINFET device includes providing a substrate including a fin structure including a plurality of fins and shallow trench isolation (STI) features between each fin of the fin structure. A first gate structure is formed over the fin structure. First gate spacers are formed on sidewalls of the first gate structure. The first gate spacers are removed while leaving portions of the first gate spacers within corners where the fin structure and the first gate structure meet. Second gate spacers are formed on sidewalls of the first gate structure. A dielectric layer is formed over the fin structure, the first gate structure, and the second gate spacers. The first gate structure and the portions of the first gate spacers are removed, thereby exposing sidewalls of the second gate spacers. A second gate structure is formed over the fin structure in a region where the first gate structure and the portions of the first gate spacers have been removed.

Method of manufacturing a FinFET device having a stepped profile

A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.

Method for fabricating a multi-gate device

A FinFET device and a method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate including a fin structure, the fin structure including a first and a second fin. The FinFET device further includes a shallow trench isolation (STI) feature disposed on the substrate and between the first and the second fins. The FinFET device further includes a gate dielectric disposed on the first and the second fins. The FinFET device further includes a gate structure disposed on the gate dielectric. The gate structure traverses the first fin, the second fin, and the STI feature between the first fin and the second fin and has a longitudinal stepped profile.

Growing community of inventors

Zhubei, Taiwan

Yuan-Shun Chao