Winbond Electronics Corporation

Winbond Electronics Corporation America

Yuan-Mou Su

Hua Zheng

A precharge circuit is operable during a standby mode to drive a word line to a low voltage level and one or more (pairs of) bit lines to a standby voltage level. The precharge circuit comprises a driver for driving the on or more bit lines to the stand by voltage level. The precharge circuit also includes a control circuit connected to a control input of the driver which control circuit receives the standby signal. The control circuit outputs a varying enable signal to the driver for varying the drive of the bit lines by the driver. The precharge circuit can include a first current limiting driver for driving the bit lines to the standby voltage level, and second driver, for driving the bit lines to the standby voltage level. The second driver has a greater switching speed, and a higher current driving capacity, than the first current limiting driver. Tie control circuit enables the second driver for a certain period of time in response to detecting an indication of a beginning of the standby mode of the standby signal.

Low word line to bit line short circuit standby current semiconductor

In accordance with a preferred embodiment of the invention, the write cycle of an SRAM column is increased. The SRAM column includes at least one SRAM cell connected to the bit line and the bit line complement of the column. Further, a pair of select transistors are located below the bottom SRAM cell, where one select transistor is connected to the bit line and the other is connected to the bit line complement. The select transistors select whether the respective bit line and bit line complement is deselected or selected. The SRAM column further includes a pair of load transistors connected between the bottom SRAM cell and the pair of select transistors, where one of the load transistors is connected to the bit line and the other load transistor is connected to said bit line complement. In operation, since the load transistors are located below the bottom cell, there is no DC current supplied by the load transistors to flow through the entire bit line and bit line complement length. Therefore, the voltage drop potential on the line is reduced which increases the write cycle speed.

SRAM with fast write capability

In accordance with a preferred embodiment of the invention, the wordline turn on voltage in an SRAM array is suppressed (e.g., maintained at or below 4.5 volts). This is accomplished by connecting a regulated voltage supply output to the wordline. The regulated voltage supply has a transfer function such that the Vccr (the output of the regulated voltage supply) does not exceed a threshold such as 4.5 volts. For example, the transfer function may be:

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Cupertino, CA, United States of America

Yuan-Mou Su