Gpower Semiconductor, Inc.

Dell Products Inc.

Yuan Li

Yi Pei

Feihang Liu

Weiyi Xie

Chuanjia Wu

Guiping Zhang

Howe Xu

Disclosed methods include sending, from a resource manager, network configuration information to each of one or more managed resources. The network configuration information may include an IP address for the resource manager, an IP address for each of the managed resources, and a predetermined timeout value. Network configurations for the resource manager and the one or more managed resources may then be set after which each managed resource may start a timer with the predetermined timeout value. If the resource manager detects successful completion of each of the network configuration operations, the resource manager may send a stop timer command to each of the managed resources. If a timeout occurs, the timeout will inform each of the managed resources that the change in network configuration was not entirely successful. The resource manager and each of the managed resources will then restore their network configurations to their previous configurations.

Method for modifying network configuration of resource manager and managed resources

The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor layer; a source electrode, a drain electrode and a gate electrode located between the source electrode and the drain electrode disposed on a side of the semiconductor layer; at least two dielectrics located between the gate electrode and the drain electrode, wherein a dielectric coefficient of a dielectric adjacent to the gate electrode is greater than that of a dielectric away from the gate electrode and adjacent to the drain electrode.

Semiconductor device and method of manufacturing the same

A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, and the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.

Field plate power device and method of manufacturing the same

The present disclosure discloses a power semiconductor device and a method for manufacturing the same. The power semiconductor device comprises: a substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, a gate electrode, and a junction termination structure located on the barrier layer. The power semiconductor device extends in a first direction from an edge of a side of the gate electrode close to the drain electrode to the drain electrode, the junction termination structure at least comprises a first region close to the gate electrode and a second region away from the gate electrode and the thickness of the first region is greater than that of the second region in a second direction perpendicular to the barrier layer. The junction termination structure can effectively improve the distribution of an electric field of the barrier layer and hence increase the breakdown voltage of the device.

Power semiconductor device and method for manufacturing the same

A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.

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Suzhou, China

Yuan Li