Ipgreat Incorporated

Other

Marvell International Limited

Integrated Device Technology, Inc.

Ipsmart Inc.

Apple Inc.

Pimic, Inc.

Yuan-Ju Chao

Ta-Shun Chu

Mansour Keramat

Lawrence Tse

King Chun Tsai

Sang Won Son

George Chien

Alireza Shirvani-Mahdavi

Vijay Srinivas

Krishnamurthy Subramanian

Chia-Tung Lee

John H Yu

A charge-injection SAR ADC device has a modified charge-injection cell (CIC), and a complementary to absolute temperature (CTAT) circuit for generating a bias voltage. The CIC and CTAT circuits cooperate to correct for process, voltage, and temperature (PVT) variation that affect SAR ADC input full scale. The CIC has been modified to have transistors that are in a cascoded relationship with transistors operating to maintain a reservoir of charge. The CTAT circuit is designed to substantially replicate the CIC, and it tracks the CIC operation to correct variations in transistor threshold voltage due to variations in PVT.

Charge-injection SAR ADC for correcting full scale PVT variation

A single-end input configurable Successive Approximation Register Analog-to-Digital Converter (SARADC) allows for the input configuration as single-ended or differential inputs without adding extra circuitry. In both configurations, the ADC maintains the same LSB voltage and output code range. Furthermore, when configured as a single-ended input, power consumption is further reduced.

Single-end input configurable differential SAR analog-to-digital converter

A method of eliminating reference voltage of Analog-to-Digital Converter to enhance faster conversion rate, achieve compact size and decrease power consumption for Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).

Apparatus and method of reference-free SAR analog-to-digital conversion

A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

Apparatus and method of enhancing linearity and expanding output amplitude for current-steering digital-to-analog converters (DAC)

Computing-in-memory utilizes memory as weight for multiply-and-accumulate (MAC) operations. Input data multiplies weights to produce output data during the operation. Method of data conversion from input data, memory element to output data is described to enhance the computing efficiency.

Method of data conversion for computing-in-memory

A method of enhancing SAR ADC conversion rate by employing a new value shifted capacitor DAC. The value shifted capacitor DAC decreases largest capacitor to improve the reference voltage settling. The reduction of capacitor is added back onto the smaller capacitor DAC to maintain the same total capacitor value. The binary search outputs are re-combined and processed to produce final binary ADC outputs. The overhead of using value shifted capacitor DAC is the extra latency needed for re-combined logic.

SAR ADC using value shifted capacitive DAC for improved reference settling and higher conversion rate

A new SARADC has two low resolution SAR (Successive Approximation Register) ADCs coupled together by an amplifier to increase the overall resolution and enhance ADC conversion rate. The gain reduction of amplifier is corrected by shifting the digital binary output position. Two SAR ADC outputs are timing aligned and summed to produce final high-resolution high conversion rate ADC output.

Digital corrected two-step SAR ADC

A method of enabling full speed test and characterization for high-speed Digital-to-Analog Converter (DAC) by employing an on-chip pattern generator. The test pattern is written to the on-chip pattern generator through a low data rate Integrated circuit (IC) interface, and the pattern generator is then enabled and coupled to DAC to facilitate full speed test for DAC. This method does not require extra input/output pin or extra process and minimize design complexity.

On-chip pattern generator for high speed digital-to-analog converter

Systems and methods are disclosed for Successive Approximation Register Analog-to-Digital Converter (SAR ADC) by coupling an ADC capacitive network coupled to a comparator; and performing binary search using a comparator output using a capacitive DAC calibration process to enhance SAR ADC linearity and performance. In one implementation, the calibration process starts with the least significant bit (LSB) capacitor calibration then proceed to higher bit capacitors until all the capacitors are calibrated. Each capacitor consists of fixed-value base capacitor and value-adjustable capacitor. The capacitor calibration logic is implemented based on the process then incorporated into SAR ADC. ADC performs capacitor calibration first before normal conversion operation. The non-ideal aspect of normal conversion operation is preserved and accounted during capacitor calibration. By employing capacitor calibration, the DAC capacitor value can be minimal to enhance settling and conversion rate, SAR ADC performance is improved.

Method of capacitive DAC calibration for SAR ADC

A method of incorporating Programmable Gain Amplifier (PGA) function into pipelined ADC for wide input range. The power consumption is saved without adding extra stage to reduce input range. The ADC input range can be adjusted on the fly using resistor bank and capacitor bank to achieve optimal system performance.

Programmable gain amplifier (PGA) embedded pipelined analog to digital converters (ADC) for wide input full scale range

A method of enhancing SAR ADC performance includes employing PVT processor to correct process, voltage and temperature (PVT) variation. The PVT processor senses process, supply voltage and temperature information then maximize the time for SAR binary search process. The PVT processor first applies coarse optimization to correct process and voltage variation then applies fine optimization to correct the temperature variation. The SAR ADC is operated at its optimized PVT condition and its performance is enhanced after PVT optimization.

Process, voltage and temperature optimized asynchronous SAR ADC

Systems and methods of restraining reverse engineering process for analog integrated circuit use techniques of adding dummy devices, device fragmentation, increasing bus width, employing different layouts for the same circuit element and mixing different types of passive devices increase complexity and makes the layout floorplan more difficult to be extracted for the reverse engineering. The system adds dummy devices and ensures the extra devices and capacitance do not affect the target circuit performance.

System and method for anti reverse engineering for analog integrated circuit

A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.

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Cupertino, CA, United States of America

Yuan-Ju Chao