Taiwan Semiconductor Manufacturing Comp. Ltd.

Yuan-Hung Chiu

Hun-Jan Tao

Ming-Huan Tsai

Li-Te S Lin

Bor-Wen Chan

Fang-Cheng Chen

Yen-Ming Chen

Chun-Fai Cheng

Hsien-Kuang Chiu

Ryan Chia-Jen Chen

Ju-Wang Hsu

An Chyi Wei

Hui OuYang

Hsiu-Hao Tsao

Chung-Shu Wu

Ying-Ya Hsu

Ching-Yu Pan

Yee-Chia Yeo

Chi-Wen Liu

Yu-Lien Huang

Chih Chieh Yeh

Tung Ying Lee

Jeng-Horng Chen

Huan-Just Lin

Shiang-Bau Wang

Shien-Yang Wu

Jeng-Ya David Yeh

Han-Yu Lin

Peng-Fu Hsu

Baw-Ching Perng

Yung-Shun Chen

Tung-Heng Shie

Han-Jan Tao

Huin-Jer Lin

Jhon Jhy Liaw

Shau-Lin Shue

Syun-Ming Jang Jang

Mei-Yun Wang

Chih-Wei Chang

Yung-Cheng Lu

Ming-Ching Chang

Jyu-Horng Shieh

Chii-Ming M Wu

Hung-Der Su

Jyh-Huei Chen

Chen-Nan Yeh

Chu-Yun Fu

Ming-Jie Huang

Mo-Chiun Yu

Mong Song Liang

Yi-Chun Huang

Wen-Kung Cheng

Hung-Ju Chien

Chao-Tzung Tsai

Mei-Hui Sung

Hui Ouyang

Hung Der Su

Haur-Ywh Chen

Yin-Lang Wang

Yui Wang

Fang-Chang Chen

Chin-Hwa Hsieh

Fang-Chen Cheng

Chu-Yan Fu

A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

FinFET device and method

A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.

Self-aligned contact and manufacturing method thereof

A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

Method of forming a contact

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Integrated circuit device with well controlled surface proximity and method of manufacturing same

Source and drain feature profile for improving device performance and method of manufacturing same

A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

Spacer layer etch method providing enhanced microelectronic device performance

A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.

Method for fabricating dual-gate semiconductor device

A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.

In-situ plasma treatment of advanced resists in fine pattern definition

A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.

Phosphoric acid free process for polysilicon gate definition

Growing community of inventors

Taipei, Taiwan

Yuan-Hung Chiu