Industrial Technology Research Institute

Computer Communication Research Labs.

Yuan-Hua Chu

Hong-Yi Huang

Kuo-Hsing Cheng

Shiun-Dian Jan

Wei-Sheng Tseng

Hwang-Cherng Chow

Jen-Chieh Liu

Chi-Chang Shuai

Ru-Jie Wang

Chun-Tsai Hung

Chih-Yuan Hsu

Ji-Jan Chen

Chih-Wei Liu

Chao-Jen Huang

Ching-Yuan Yang

Yu Chi Lee

Wei-Ming Chiu

Tay-Jyi Lin

Nai-Chen Cheng

Pi-Cheng Hsiao

Shih-Hao Ou

Fang-Chih Chu

Xiang-Sheng Deng

Chou-Kun Lin

Ruei-lun Pu

Yi-Jui Tsai

Hung-Chang Chu

Li-Wei Huang

Ruei-Iun Pu

Tai-Ji Lin

Sheng-Dar Wu

Ching-Chieh Wu

Pin-Chen Wang

Tien-Wei Hsieh

Jian-Hong Shen

A thermoelectric converter includes a battery box, an outer box and a connecting ring. The battery box has a bottom case, a battery disposed in the bottom case, a battery circuit board electrically connected to the battery, and an application circuit board disposed at one end of the bottom case. The outer box has a heat sink surrounding and covering the battery box, a thermoelectric module electrically connected to the battery circuit board with the thermoelectric module electrically connected to the battery through the battery circuit board, a heat conducting plate overlying the thermoelectric module and configured to conduct thermal energy from ambient environment to the thermoelectric module for the thermoelectric module to absorb the thermal energy and convert the thermal energy to electricity, and a non-metal adiabatic frame surrounding the thermoelectric module and configured to prevent the thermal energy from being dissipated to the ambient environment.

Thermoelectric converter

A multicore interface with dynamic task management capability and a task loading and offloading method thereof are provided. The method disposes a communication interface between a micro processor unit (MPU) and a digital signal processor (DSP) and dynamically manages tasks assigned by the MPU to the DSP. First, an idle processing unit of the DSP is searched, and then one of a plurality of threads of the task is assigned to the processing unit. Finally, the processing unit is activated to execute the thread. Accordingly, the communication efficiency of the multicore processor can be effectively increased while the hardware cost can be saved.

Multicore interface with dynamic task management capability and task loading and offloading method thereof

An embodiment of a processing device includes a function unit and a control unit. The function unit receives input data and performs a specific operation to the input data to generate result data. The control unit receives the result data and generates an output signal. The control unit latches the result data according to a first clock signal to generate first data and latches the result data according to a second clock signal to generate second data. The control unit compares the first data with the second data to generate a control signal and selects the first data or the second data to serve as data of the output signal according to the control signal. The second clock signal is delayed from the first clock signal by a predefined time period.

Processing device for determining whether to output a first data using a first clock signal or a second data using delay from the first clock signal according to a control signal

An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.

Apparatus for clock skew compensation

A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.

Clock generator and delta-sigma modulater thereof

An onion waveform generator and a spread spectrum clock generator (SSCG) using the same are provided. The onion waveform generator includes a value generation unit and an accumulating unit. The value generation unit outputs a counting value. The accumulating unit accumulates the counting value to output a waveform value. The accumulating unit switches from an increasing mode to a decreasing mode if the waveform value is a third boundary value, and the accumulating unit switches from the decreasing mode to the increasing mode if the waveform value is a fourth boundary value.

Onion waveform generator and spread spectrum clock generator using the same

A signal transceiver apparatus suitable for a wired signal transceiver system includes a differential signal transmitter, an impendence matching control module and a signal receiver. The signal transmitter has an output terminal which is connected to a transceiver wire. The signal transmitter includes a first impendence tuner and is used to receive a control signal so as to tune impendence of the first impendence tuner according to the control signal. Moreover, the impendence matching control module generates the control signal according to a compare signal and a lock signal. Besides, the signal receiver generates the lock signal and the compare signal according to a compare result between a current flowing through the first impendence tuner and a reference current.

Signal transceiver apparatus and system

A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same

A voltage generating apparatus including a voltage generator and a current splitter is provided. The voltage generator has an output node, and generates a first output voltage from the output node. The first output voltage rises when the temperature rises and the current flowing from the output end of the voltage generator is fixed. And the first output voltage drops when the temperature is fixed and the current flowing from the output node of the voltage generator rises. The current splitter is used for increasing the current flowing through the current splitter when the temperature rises. Therefore, the rise of the first output voltage of the voltage generator will be restrained, and the temperature compensation can be achieved.

Voltage generating apparatus

A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase detector includes digital delay components for producing delay outputs according to the counting signals and thereby detecting a pulse input signal. The Vernier detector includes digital delay components for detecting the remainder of the pulse input signal according to the difference between the delay outputs produced by the subtracter.

Time-to-digital converter apparatus

Clock generator, multimodulus frequency divider and deta-sigma modulater thereof

A spread spectrum clock generating apparatus is disclosed. The spread spectrum clock generating apparatus includes a phase lock loop module and a spread spectrum module. The phase lock loop module is used for dynamically tuning frequency of an output clock. The spread spectrum module includes a counter, a plurality of delta-sigma counters and a data shifter. These delta-sigma counters accumulate input signals, and enable a first overflow signal while accumulation of a last stage delta-sigma counter is overflowed. The frequency of the output clock can be tuned dynamically according to the first overflow signal, and the spectrum of the output clock can be spread.

Spread spectrum clock generating apparatus

A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current.

Bulk input current switch logic circuit

Growing community of inventors

Hsinchu County, Taiwan

Yuan-Hua Chu