Taiwan Semiconductor Manufacturing Comp. Ltd.

Yuan-Chih Hsieh

Chia-Shiung Tsai

Lan-Lin Chao

Hung-Hua Lin

Ping-Yin Liu

Chun-Wen Cheng

Xin-Hua Huang

Jung-Huei Peng

Li-Cheng Chu

Lee-Chuan Tseng

Ming-Tung Wu

Yi-Ren Wang

Chung-Yen Chou

Hsin-Ting Huang

Chih-Jen Chan

Gwo-Yuh Shiau

Chung-Yi Yu

Martin Liu

Che-Ming Chang

Richard Chu

Shih-Chang Liu

Hsing-Lien Lin

Shang-Ying Tsai

Shing-Chyang Pan

Shih-Wei Lin

Shih-Chi Fu

Chia-Ming Hung

Yi-Chien Wu

Chia-Hua Chu

Hsun-Chung Kuang

Xiaomeng Chen

Chung-Hsien Lin

Ming-Chyi Liu

Wen-Chuan Tai

Hsiang-Fu Chen

Chih-Ming Chen

Tzu-Hsuan Hsu

Chang-Ming Wu

Kuei-Sung Chang

Feng-Jia Shiu

Fei-Lung Lai

Yao-Te Huang

Shao-Chi Yu

Hung-Chia Tsai

Liang-Lung Yao

Ru-Liang Lee

Te-Hao Lee

Mingo Liu

Dun-Nian Yaung

Chun-Ren Cheng

Ming Chyi Liu

Yi-Hsien Chang

Chi-Hsin Lo

Hsiao-Chin Tuan

Yuan-Hung Liu

Allen Timothy Chang

Hua-Shu Ivan Wu

Kai-Chih Liang

Alex Kalnitsky

Ching-Ray Chen

Tsung-Hsun Huang

Tsung-Mu Lai

Uway Tseng

Liang-Kai Han

Fa-Yuan Chang

Ching-Chung Pai

Nick Y M Shen

Xin-Chung Kuang

Chin-Hsiang Ho

Chu-Wei Cheng

Shih-Chu Fu

Hung Hua Lin

Li-Chen Chu

H T Huang

Lan-Lin

A layer stack is formed over a conductive material portion located on a substrate. The layer stack contains a first silicon oxide layer, a silicon nitride layer formed by chemical vapor deposition, and a second silicon oxide layer. A patterned etch mask layer including an opening is formed over the layer stack. A via cavity extending through the layer stack and down to the conductive material portion is formed by isotropically etching portions of the layer stack underlying the opening in the patterned etch mask layer using an isotropic etch process. A buffered oxide etch process may be used, in which the etch rate of the silicon nitride layer is less than, but is significant enough, compared to the etch rate of the first silicon oxide layer to provide tapered straight sidewalls on the silicon nitride layer. An optical device including a patterned layer stack can be provided.

Methods for patterning a silicon oxide-silicon nitride-silicon oxide stack and structures formed by the same

A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Integrate rinse module in hybrid bonding platform

The present disclosure provides a structure and method of fabricating the structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.

Semiconductor MEMS structure

In some embodiments, the present disclosure relates to a piezomicroelectromechanical system (piezoMEMS) device that includes a second piezoelectric layer arranged over the first electrode layer. A second electrode layer is arranged over the second piezoelectric layer. A first contact is arranged over and extends through the second electrode layer and the second piezoelectric layer to contact the first electrode layer. A dielectric liner layer is arranged directly between the first contact and inner sidewalls of the second electrode layer and the second piezoelectric layer. A second contact is arranged over and electrically coupled to the second electrode layer, wherein the second contact is electrically isolated from the first contact.

Pizoelectric MEMS device with electrodes having low surface roughness

Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.

Microelectromechanical systems device having a mechanically robust anti-stiction/outgassing structure

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.

Conductive bond structure to increase membrane sensitivity in MEMS device

A microstructure may be provided by forming a metal layer such as a molybdenum layer over a substrate. An aluminum nitride layer is formed on a top surface of the metal layer. A surface portion of the aluminum nitride layer is converted into a continuous aluminum oxide-containing layer by oxidation. A dielectric spacer layer may be formed over the continuous aluminum oxide-containing layer. Contact via cavities extending through the dielectric spacer layer, the continuous aluminum oxide containing layer, and the aluminum nitride layer and down to a respective portion of the at least one metal layer may be formed using etch processes that contain a wet etch step while suppressing formation of an undercut in the aluminum nitride layer. Contact via structures may be formed in the contact via cavities. The microstructure may include a micro-electromechanical system (MEMS) device containing a piezoelectric transducer.

Undercut-free patterned aluminum nitride structure and methods for forming the same

The present disclosure provides a structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.

The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

Packaging method and associated packaging structure

Various embodiments of the present disclosure are directed towards a method for manufacturing an integrated chip, the method comprises forming an interconnect structure over a semiconductor substrate. An upper dielectric layer is formed over the interconnect structure. An outgas layer is formed within the upper dielectric layer. The outgas layer comprises a first material that is amorphous. A microelectromechanical systems (MEMS) substrate is formed over the interconnect structure. The MEMS substrate comprises a moveable structure directly over the outgas layer.

Structure for microelectromechanical systems (MEMS) devices to control pressure at high temperature

The present disclosure provides a micro electro mechanical system (MEMS) structure, including a device substrate having a first region and a second region different from the first region, a capping substrate bonded over the device substrate, a first cavity in the first region and between the device substrate and capping substrate, wherein the first cavity has a first cavity pressure, a second cavity in the second region and between the device substrate and capping substrate, wherein the second cavity has a second cavity pressure lower than the first cavity pressure, a passivation layer in the first cavity, an outgassing material over the passivation layer, wherein the outgassing material comprises a top surface and a sidewall exposed to the first cavity.

MEMs using outgassing material to adjust the pressure level in a cavity

A system includes a semiconductor substrate having a first cavity. The semiconductor substrate forms a pedestal adjacent the first cavity. A device overlays the pedestal and is bonded to the semiconductor substrate by metal within the first cavity. A plurality of second cavities are formed in a surface of the pedestal beneath the device, wherein the second cavities are smaller than the first cavity. In some of these teachings, the second cavities are voids. In some of these teachings, the metal in the first cavity comprises a eutectic mixture. The structure relates to a method of manufacturing in which a layer providing a mask to etch the first cavity is segmented to enable easy removal of the mask-providing layer from the area over the pedestal.

Segmented pedestal for mounting device on chip

Growing community of inventors

Hsinchu, Taiwan

Yuan-Chih Hsieh