International Business Machines Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Yuan-Chen Sun

Bernard S Meyerson

Jack Allan Mandelman

Louis L Hsu

Jack Oon Chu

Tze-Chiang Chen

Lia Krusin-Elbaum

Chao-Chieh Tsai

Denny D Tang

Yuan Taur

Chin-Hsiung Ho

Pong-Fei Lu

Richard Joseph Gambino

Matthew R Wordeman

Praveen Chaudhari

Robert B Laibowitz

Roger Hilsen Koch

Joachim Norbert Burghartz

George A Sai-Halasz

James H Comfort

Mohamed O Aboelfotoh

Eti Ganin

Janes H Comfort

In a Field Effect Transistor (FET) with a semiconductor channel the use of a high T oxide superconductor material in the gate electrode provides both control of parasitic resistance and capacitance and a proper work function when operated at a temperature below the T . The 1-2-3 compound oxide superconductors with the general formula Y Ba Cu O where y is approximately 0.1 have the ability in use in FET's to provide convenient work functions, low resistance and capacitance, and to withstand temperatures encountered in processing as the FET is being manufactured.

Superconductor gate semiconductor channel field effect transistor

A method of forming borderless contacts and vias is disclosed. Borders which are conventionally provided in aligning contacts and vias to device and/or metal regions in a semiconductor device take up too much valuable real estate on semiconductor substrates, and hence reduce productivity of the products. By employing a hard-mask of this invention, and a specific sequence of process steps, alignment can be achieved without the need for borders. First, a thin nitride layer is deposited on an insulating layer formed over a substructure of a substrate having device and/or metal regions. The hard-mask is patterned with metal line openings, and a photoresist layer is formed with contact or via pattern over the already patterned hard-mask. The contact/via openings are etched into the dielectric layer until the substructure is reached. The hole openings are filled plug metal and then partially etched back, leaving a plug in the hole opening. The line trench is etched further into the dielectric layer until metal plug is reached. The trench is then filled with metal, such as aluminum-copper or copper and the excess is removed by chemical-mechanical polishing. Thus, a borderless and self-aligned interconnect comprising plug and metal line is formed.

Borderless contact

A dual damascene process is disclosed for forming contact and via interconnects without borders. A nitride layer is first formed on a dielectric layer to function as a hard-mask. Metal line trench is first etched into the nitride layer and then into the dielectric layer. Then, a second photoresist layer is used to pattern contact or via hole over line trench opening and the dielectric layer is further etched through the line trench into the dielectric layer until the substructure of the substrate is reached. It is disclosed that by using the nitride layer as a hard-mask, the registration or alignment tolerance between the contact/via hole pattern and the metal line pattern can be relaxed substantially and not use a border as is conventionally practiced in order to assure proper registration between the patterns. The borderless interconnect is achieved by filling the composite line opening and the hole opening with metal and chemical mechanical polishing. The process enables cost reduction and productivity in the semiconductor manufacturing line.

Dual damascene interconnect process with borderless contact

A low temperature annealed Cu silicide or germanide layer on the surface of a single crystalline semiconductor substrate of Si or Ge is used in interconnection metallization for integrated circuits. The Cu silicide or germanide layer is preferably formed by heating Cu deposited on a Si or Ge substrate up to about 200.degree. C. for about 30 minutes. The layer demonstrates superior (near ideal) current/voltage characteristics and can be used as a high temperature (600-800.degree. C.) stable Ohmic/Schottky contact to Si or as a Cu diffusion barrier. Additional embodiments involve a Cu layer on a Ge layer on Si substrate, a Cu layer on a Si.sub.x Ge.sub.1-x layer on a substrate, and the use of an intermediate layer of a refractory metal such as W.

Multilevel electronic structures containing copper layer and

A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.

Vertical double-gate field effect transistor

A dual gate thin film or SOI MOSFET device having a sufficiently thin body thickness with one or more semiconductor channel layer(s) sandwiched by semiconductor layers having a different energy band structure to automatically confine carriers to the channel layer(s) without the need for channel grading or modulation doping. Preferred embodiments employ strained layer epitaxy having Si/SiGe/Si or SiGe/Si/SiGe semiconductor layers.

SiGe thin film or SOI MOSFET and method for making the same

This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-aligned elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferable polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.

Low capacitance bipolar junction transistor and fabrication process

This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferably polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.

Process for fabricating low capacitance bipolar junction transistor

Growing community of inventors

Katonah, NY, United States of America

Yuan-Chen Sun