Enkris Semiconductor, Inc.

Yu Zhu

Kai Cheng

Peng Xiang

The present application provides a semiconductor structure and a method for manufacturing the same, which solves a problem that an existing semiconductor structure is difficult to deplete a carrier concentration of a channel under a gate to realize an enhancement mode device. The semiconductor structure includes: a channel layer and a barrier layer superimposed in sequence, wherein a gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region, wherein the plurality of trenches extend into the channel layer; and a P-type semiconductor material filling the plurality of trenches.

Semiconductor structure and method for manufacturing the same

A semiconductor structure includes a heterojunction, including at least two sets of channel layers and barrier layers stacked sequentially; a first p-type semiconductor, disposed in a gate region of the heterojunction and extended to a bottom of the heterojunction; and a second p-type semiconductor, disposed on the gate region of the heterojunction. By providing a heterojunction including at least two sets of channel layers and barrier layers stacked sequentially, multilayer 2DEG is realized by using multilayer channel layers and barrier layers to increase the concentration of 2DEG, thereby reducing the resistance. Since a first p-type semiconductor is disposed in a gate region of the heterojunction, the p-type semiconductor materials in the first p-type semiconductor are used to deplete the 2DEG to realize normally-off and increase the threshold voltage.

Heterostructure including alternating sets of channel and barrier layers

Disclosed are a semiconductor structure and a manufacturing method therefor, solving the problem that it is difficult for an existing semiconductor structure to deplete a carrier concentration of a channel under a gate so as to achieve an enhancement-mode device. The semiconductor structure comprises: a channel layer and a barrier layer stacked in sequence. A gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region. The plurality of trenches are extended into the channel layer; and a stress applying material filled in the plurality of trenches. A lattice constant of the stress applying material is greater than that of the channel layer.

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Nantong, China

Yu Zhu